S5335 datasheet(85/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

Data Sheet

INITIALIZATION

All PCI bus agents and bridges are required to imple-

ment PCI Configuration Registers. When multiple PCI

devices are present, these registers must be unique to

each device in the system. The specified PCI proce-

dure for uniquely selecting a device’s configuration

space involves a dedicated signal, called IDSEL, con-

nected to each motherboard PCI bus device and PCI

slot.

The host executes configuration cycles after reset to

each device on the PCI bus. The configuration regis-

ters provide information on PCI agent operation and

memory or I/O space requirements. These allow the

PCI BIOS to enable the device and locate it within sys-

tem memory or I/O space.

After a PCI reset, the S5335 can be configured for a

specific application by downloading device setup infor-

mation from an external non-volatile memory into the

device Configuration Registers. The S5335 can also

be used in a default configuration, with no external

boot device.

When using a non-volatile boot memory to customize

operation, 64 bytes are required for S5335 setup infor-

mation. The rest of the boot device may be used to

implement an Expansion BIOS, if desired. Some of the

setup information is used to initialize the S5335 PCI

Configuration Registers, other information is not down-

loaded into registers, but is used to define S5335

operation (FIFO interface, Pass-Thru operation, etc.).

PCI RESET

Immediately following the assertion of the PCI RST#

signal, the Add-On reset output SYSRST# is asserted.

Immediately following the deassertion of RST#,

SYSRST# is deasserted. The Add-On reset output

may be used to initialize state machines, reset Add-On

microprocessors, or reset other Add-On logic devices.

All S5335 Operation Registers and Configuration Reg-

isters are initialized to their default states at reset. The

default values for the Configuration Registers may be

overwritten with the contents of an external nv boot

memory during device initialization, allowing a custom

device configuration. Configuration accesses by the

host CPU to the S5335 produce PCI bus wait states

until one of the following events occurs:

•

The S5335 identifies that there is no valid boot

memory (and default Configuration Register

values are used).

•

The S5335 finishes downloading all configura-

tion information from a valid boot memory.

LOADING FROM BYTE-WIDE NV MEMO-

RIES

The SNV input on the S5335 indicates what type of

external boot-load device is present (if any). If SNV is

tied low, a byte-wide nv memory is assumed. In this

case, immediately after the PCI bus reset is deas-

serted, the address 0040h is presented on the nv

memory interface address bus EA[15:0]. Eight PCI

clocks later (240 ns at 33 MHz), data is read from the

nv memory data bus EQ[7:0] and address 0041h is

presented. After an additional eight PCI clocks, data is

again read from EQ7:0. If both accesses read are all

ones (FFh), it implies an illegal Vendor ID value, and

the external nv memory is not valid or not present. In

this situation, the AMCC default configuration values

are used.

If either of the accesses to address 0040h and 0041h

contain zeros (not FFh), the next accesses are to loca-

tions 0050h, 0051h, 0052h, and 0053h. At these

locations, the data must be C0h (or C1h or C2h), FFh,

E8h, and 10h, respectively, for the external nv memory

to be valid. Once a valid external nv memory has been

recognized, it is read, sequentially, from location

0040h to 007Fh. The appropriate data is loaded into

the PCI Configuration Registers as described in Chap-

ter 4. Some of the boot device data is not downloaded

into Configuration Registers, but is used to enable fea-

ture s an d co n f i g u r e S5 33 5 op eratio n. Up o n

completion of this procedure, the boot-load sequence

terminates and PCI configuration accesses to the

S5335 are acknowledged with the PCI Target Ready

(TRDY#) output.

Table 51 lists the required nv memory contents for a

valid configuration nv memory device.

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