S5335 datasheet(97/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

Data Sheet

Master-Initiated Termination

Occasionally, a PCI transfer must be terminated by the

initiator. Typically, the initiator terminates a transfer

upon the successful completion of the transfer. Some-

times, the initiator’s bus mastership is relinquished by

the bus arbiter (GNT# is removed), often because

another device requires bus ownership. This is called

initiator preemption and is discussed in later Sections.

When the S5335 is an initiator and does not observe a

DEVSEL# response to its assertion of FRAME#, it ter-

minates the cycle (master abort).

Normal Cycle Completion

A successful data transfer occurs when both the initia-

tor and target assert their respective ready signals,

IRDY# and TRDY#. The last data phase is indicated

by the initiator when FRAME# is deasserted during a

data transfer. A normal cycle completion occurred if

the target does not assert STOP#. Figure 51 shows

the signal relationships defining a normal transfer

completion.

Figure 50. Single Data Phase PCI Bus Write of S5335 Registers (S5335 as Target)

Figure 51. Master-Initiated, Normal Completion (S5335 as either Target or Initiator)

PCI CLOCK

FRAME #

AD[31:0]

C/BE[3:0]#

IRDY#

TRDY#

DEVSEL#

ST O P#

ADDRESS

DATA 1

BYTE EN 1

BUSCOMMAND

(I)

(T)

(I)

BYTE EN 2

DATA 2

DATA

TRANSFER #1

DATA

TRANSFERRED

(T)

IF BURST

ATTEMPT

(I) = DRIVEN BY INITIATOR

(T) = DRIVEN BY TARGET

PCI CLOCK

FRAME #

IRDY#

TRDY#

DEVSEL#

(T)

(I)

(T)

NORMAL

COMPLETION

(I)

(I) = DRIVEN BY INITIATOR

(T) = DRIVEN BY TARGET

STOP#

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