S5335 datasheet(20/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

Data Sheet

Table 4. Address and Data Pins — PCI Local Bus

Signal

Type

Description

AD[31:00]

t/s

Local Bus Address/Data lines. Address and data are multiplexed on the same pins. Each bus opera-

tion consists of an address phase followed by one or more data phases. Address phases are identified

when the control signal, FRAME#, is asserted. Data transfers occur during those clock cycles in which

control signals IRDY# and TRDY# are both asserted.

C/BE[3:0]#

t/s

Bus Command and Byte Enables. These are multiplexed on the same pins. During the address phase

of a bus operation, these pins identify the bus command, as shown in the table below. During the data

phase of a bus operation, these pins are used as Byte Enables, with C/BE[0]# enabling byte 0 (least

significant byte) and C/BE[3]# enabling byte 3 (most significant byte).

C/BE[3:0]#

Description (during address phase)

Interrupt Acknowledge

Special Cycle

I/O READ

I/O WRITE

Reserved

Memory Read

Memory Write

Reserved

Configuration Read

Configuration Write

MEMORY READ - Multiple

Dual Address Cycle

Memory Read Line

Memory Write and Invalidate

PAR

t/s

Parity. This signal is even parity across the entire AD[31:00] field along with the C/BE[3:0]# field. The

parity is stable in the clock following the address phase and is sourced by the master. During the data

phase for write operations, the bus master sources this signal on the clock following IRDY# active;

during the data phase for read operations, this signal is sourced by the target and is valid on the clock

following TRDY# active. The PAR signal therefore has the same timing as AD[31:00}, delayed by one

clock.

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