S5335 datasheet(98/189 Pages) AMCC

98 / 189 page

S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

Data Sheet

Initiator Preemption

A PCI initiator (bus master) is said to be preempted

when the system platform deasserts the initiator’s bus

grant signal, GNT#, while it still requests the bus

(REQ# asserted). This situation occurs if the initiator’s

latency timer expires and the system platform (bus

arbitrator) has a bus master request from another

device. The S5335 Master Latency Timer register con-

trols the S5335 responsiveness to the removal of a

bus grant (preemption). The presence of a Master

Latency Timer register can cause two preemption

situations:

1. Removal of GNT# when the latency timer is non-

zero (S5335 is guaranteed to still “own the bus”).

2. Removal of the GNT# after the latency timer has

expired.

The first situation is depicted in Figure 52, when the

latency timer has not expired. Preemption with a zero

or expired latency timer is shown in Figure 53.

Figure 52. Master Initiated Termination Due to Preemption and Latency Timer Active (S5335 as Master)

Figure 53. Master Initiated Termination Due to Preemption and Latency Timer Expired (S5335 as Master)

PCI CLOCK

GNT #

FRAME

IRDY#

TRDY#

S5335

LATENCY

TIMER

(T)

(I)

PREEMPTION

DATA

TRANSFERRED

(I)

DATA

TRANSFERRED

DATA

TRANSFERRED

DATA

TRANSFERRED

TIMEOUT

SENSED

(I) = DRIVEN BY INITIATOR

(T) = DRIVEN BY TARGET

PCICLOCK

GNT#

FRAME

IRDY#

TRDY#

LATENCY

TIMER

(T)

(I)

PREEMPTION

DATA

TRANSFERRED

(I)

(I) =DRIVEN BY INITIATOR

(T) = DRIVEN BY TARGET

S5335

S5335 Datasheet(PDF) 98 Page - Applied Micro Circuits Corporation

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