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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

Data Sheet

Built-In Self-test Register (BIST)

The Built-In Self-Test (BIST) register permits the

implementation of custom, user-specific diagnostics.

This register has four fields as depicted in Figure 16.

Bit 7, when set signifies that this device supports a

built-in self test. When bit 7 is set, writing a 1 to bit 6

will commence the self test. In actuality, writing a 1 to

bit 6 produces an interrupt to the Add-On interface. Bit

6 will remain set until cleared by a write operation to

this register from the Add-On bus interface. When bit 6

is reset it is interpreted as completion of the self-test

and an error is indicated by a non-zero value for the

completion code (bits 3:0).

Figure 16. Built-In Self Test Register

Built-in Self-Test

Address Offset:

0Fh

Power-up value:

00h

Boot-load:

External nvRAM/EPROM offset 04Fh

Attribute:

D7, D5-0 Read Only, D6 as PCI bus

write only

Size:

8 bits

Table 36. Built-In Self-Test Register

Bit

Description

BIST Capable. This bit indicates that the Add-On device supports a built-in self-test when a one is returned. A zero

should be returned if this self test feature is not desired. This field is read only from the PCI interface.

Start BIST. Writing a 1 to this bit indicates that the self-test should commence. This bit can only be written when bit 7 is

a 1. When bit 6 becomes set, an interrupt is issued to the Add-On interface. Other than through the reset pin, Bit 6 can

only be cleared by a write to this element from the Add-On bus interface as outlined in Section 6.5. The PCI bus spec-

ification requires that this bit be cleared within 2 seconds after being set, or the device will be failed.

5:4

Reserved. These bits are reserved. This field will always return zeros.

3:0

Completion Code. This field provides a method for detailing a device-specific error. It is considered valid when the Start

BIST field (bit 6) changes from 1 to 0. An all-zero value for the completion code indicates successful completion.

Bit

Value

User defined

Completion Code (RO)

Reserved (RO)

Start BIST (WO)

BIST Capable (RO)

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