S5335 datasheet(92/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

Data Sheet

PCI BUS INTERFACE

This section describes the various events which occur

on the S5335 PCI bus interface. Since the S5335 con-

troller functions as both a target (slave) and an initiator

(master), signal timing detail is given for both situa-

tions this Section presents the signal relationships

involved in performing basic read or write transfers on

the PCI bus and also describes the different ways

these cycles may complete.

PCI BUS TRANSACTIONS

Because the PCI bus has multiplexed address/data

pins, AD[31:0], each PCI bus transaction consists of

two phases: Address and Data. An address phase is

defined by the clock period when the signal FRAME#

transitions from inactive (high) to active (low). During

the address phase, a bus command is also driven by

the initiator on signal pins C/BE[3:0]#. If the command

indicates a PCI read, the clock cycle following the

address phase is used to perform a “bus turn-around”

cycle. A turn-around cycle is a clock period in which

the AD bus is not driven by the initiator or the target

device. This is used to avoid PCI bus contention. For a

write command, a turn-around cycle is not needed,

and the bus goes directly from the address phase to

the data phase.

All PCI bus transactions consist of an address phase

(described above), followed by one or more data

phases. The address phase is only one PCI clock long

and the bus cycle information (address and command)

is latched internally by the S5335. The number of data

phases depends on how many data transfers are

desired or are possible with a given initiator-target pair.

A data phase consists of at least one PCI clock.

FRAME# is deasserted to indicate that the final data

phase of a PCI cycle is occurring. Wait states may be

added to any data phase (each wait state is one PCI

clock).

The PCI bus command presented on the C/BE[3:0]#

pins during the address phase can represent 16 possi-

ble states. Table 54 lists the PCI commands and

identifies those which are supported by the S5335

controller as a target and those which may be pro-

duced by the S5335 controller as an initiator. A “Yes”

in the “Supported As Target” column in Table 54 indi-

ca tes t he S5 33 5 co nt ro lle r as ser ts the sign al

DEVSEL# when that command is issued along with

the appropriate PCI address. Two commands are sup-

ported by the S5335 controller as an initiator: Memory

Read and Memory Write.

The completion or termination of a PCI cycle can be

signaled in several ways. In most cases, the comple-

tion of the final data phase is indicated by the

assertion of ready signals from both the target

(TRDY#) and initiator (IRDY#) while FRAME# is inac-

tive. In some cases, the target is not be able to

continue or support a burst transfer and asserts the

STOP# signal. This is referred to as a target discon-

nect. There are also cases where an addressed

device does not exist, and the signal DEVSEL# never

becomes active. When no DEVSEL# is asserted in

response to a PCI cycle, the initiator is responsible for

ending the cycle. This is referred to as a master abort.

The bus is returned to the idle phase when both

FRAME# and IRDY# are deasserted.

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