S5335 datasheet(69/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

Data Sheet

Read versus Write priority. This bit controls the priority of read transfers over write transfers. When set to a 1 with bit

D8 as zero this indicates that read transfers always have priority over write transfers; when set to a one with D8 as

one, this indicates that transfer priorities will alternate equally between read and writes.

Reserved. Always zero.

Write Transfer Enable. This bit must be set to a one for PCI bus master write transfers to take place. Writing a zero

to this location will suspend an active transfer. An active transfer is one in which the transfer count is not zero.

Write FIFO management scheme. When set to a one this bit causes the controller to refrain from requesting the PCI

bus unless it has four or more FIFO locations filled. Once the S5335 controller is granted the PCI bus or is in pos-

session of the bus due to the write channel, this constraint is not meaningful. When this bit is zero the controller will

request the PCI bus if it has at least one valid FIFO word.

Write versus Read priority. This bit controls the priority of write transfers over read transfers. When set to a one with

bit D12 as zero this indicates that write transfers always have priority over read transfers. This combination is not

allowed, data integrity may be compromised. When set to a one with D12 as one, this indicates that transfer priori-

ties will alternate equally between writes and reads.

Add-On to PCI Transfer Count Equal Zero (RO). This bit is a one to signify that the write transfer count is all zeros.

PCI to Add-On Transfer Count Equals Zero (RO). This bit is a one to signify that the read transfer count is all zeros.

Add-On to PCI FIFO Empty. This bit is a one when the Add-On to PCI bus FIFO is completely empty.

Add-On to PCI 4+ words. This bit is a one when there are four or more FIFO words valid within the Add-On to PCI

bus FIFO.

Add-On to PCI FIFO Full. This bit is a one when the Add-On to PCI bus FIFO is completely full.

PCI to Add-On FIFO Empty. This bit is a one when the PCI bus to Add-On FIFO is completely empty.

PCI to Add-On FIFO 4+ spaces. This bit signifies that there are at least four empty words within the PCI to Add-On

FIFO.

PCI to Add-On FIFO Full. This bit is a one when the PCI bus to Add-On FIFO is completely full.

Table 46. Bus Master Control/Status Register (Continued)

Bit

Description

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