SH7616 datasheet(184/935 Pages) RENESAS

184 / 935 page

Section 5 Interrupt Controller (INTC)

Rev. 2.00 Mar 09, 2006 page 158 of 906

REJ09B0292-0200

Vectors

Interrupt

Priority

within

Interrupt Source

Vector

No.

Vector

Table

Address

Order

(Initial

Value)

IPR (Bit

Numbers)

IPR

Setting

Unit

VCR (Bit

Numbers)

Default

Priority

SIOF

RERI0

0–127*

VBR +

15–0 (0)

IPRE

High

VCRP (14–8) High

TERI0

0–127*

(vector No.

(11–8)

↑

VCRP (6–0)

↑

RDFI0

0–127*

× 4)

↓

VCRQ (14–8)

TDEI0

0–127*

Low

VCRQ (6–0)

SIO1

RERI1

0–127*

15–0 (0)

IPRE

High

VCRR (14–8)

TERI1

0–127*

(7–4)

↑

VCRR (6–0)

RDFI1

0–127*

↓

VCRS (14–8)

TDEI1

0–127*

Low

VCRS (6–0)

SIO2

RERI2

0–127*

15–0 (0)

IPRE

High

VCRT (14–8)

TERI2

0–127*

(3–0)

↑

VCRT (6–0)

RDFI2

0–127*

↓

VCRU (14–8)

TDEI2

0–127*

Low

VCRU (6–0)

↓

Reserved

128–255 —

—

Low

Notes: 1. An external vector number fetch can be performed without using the auto-vector

numbers shown in this table. The external vector numbers are 0–127.

2. Vector numbers are set in the on-chip vector number register.

3. REF is the refresh control unit within the bus state controller.

4. Set to IRL1–IRL15 or IRQ0–IRQ3 by the EXIMD bit in ICR.

5. In the SH7616, VCRB is a reserved register and must not be accessed.

6. The E-DMAC interrupt (EINT) is the OR of those of the 19 interrupt sources in the

EtherC/E-DMAC status register (EESR) that are enabled by the EtherC/E-DMAC status

interrupt permission register (EESIPR). As the three status bits in the EtherC status

input to the INTC as the OR of a maximum of 22 interrupt sources.

SH7616 Datasheet(PDF) 184 Page - Renesas Technology Corp

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