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SH7616 Datasheet(PDF) 186 Page - Renesas Technology Corp |
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SH7616 Datasheet(HTML) 186 Page - Renesas Technology Corp |
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186 / 935 page ![]() Section 5 Interrupt Controller (INTC) Rev. 2.00 Mar 09, 2006 page 160 of 906 REJ09B0292-0200 5.3.2 Interrupt Priority Level Setting Register B (IPRB) Interrupt priority level setting register B (IPRB) is a 16-bit read/write register that assigns priority levels from 0 to 15 to on-chip peripheral module interrupts. IPRB is initialized to H'0000 by a reset. It is not initialized in standby mode. Bit: 15 14 13 12 11 10 9 8 E-DMAC IP3 E-DMAC IP2 E-DMAC IP1 E-DMAC IP0 FRTIP3 FRTIP2 FRTIP1 FRTIP0 Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 654 321 0 — ——— ——— — Initial value: 0 0 0 0 0 0 0 0 R/W: R RRR RRR R Bits 15 to 12—Ethernet Controller Direct Memory Access Controller (E-DMAC) Interrupt Priority Level 3 to 0 (E-DMACIP3–E-DMACIP0): These bits set the ethernet controller direct memory access controller (E-DMAC) interrupt priority level. There are four bits, so levels 0–15 can be set. Bits 11 to 8—16-Bit Free-Running Timer (FRT) Interrupt Priority Level 3 to 0 (FRTIP3– FRTIP0): These bits set the 16-bit free-running timer (FRT) interrupt priority level. There are four bits, so levels 0–15 can be set. Bits 7 to 0—Reserved: These bits are always read as 0. The write value should always be 0. |
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