SH7616 datasheet(185/935 Pages) RENESAS

185 / 935 page

Section 5 Interrupt Controller (INTC)

Rev. 2.00 Mar 09, 2006 page 159 of 906

REJ09B0292-0200

5.3

5.3.1

Interrupt Priority Level Setting Register A (IPRA)

Interrupt priority level setting register A (IPRA) is a 16-bit read/write register that assigns priority

levels from 0 to 15 to on-chip peripheral module interrupts. IPRA is initialized to H'0000 by a

reset. It is not initialized in standby mode. Unless otherwise specified, ‘reset’ refers to both power-

on and manual resets throughout this manual.

Bit:

————

DMAC

IP3

DMAC

IP2

DMAC

IP1

DMAC

IP0

Initial value:

00000000

R/W:

RRRR

R/W

Bit:

76543210

WDT

IP3

WDT

IP2

WDT

IP1

WDT

IP0

————

Initial value:

00000000

R/W:

R/W

RRRR

Bits 15 to 12—Reserved: These bits are always read as 0. The write value should always be 0.

Bits 11 to 8—Direct Memory Access Controller (DMAC) Interrupt Priority Level 3 to 0

(DMACIP3–DMACIP0): These bits set the direct memory access controller (DMAC) interrupt

priority level. There are four bits, so levels 0–15 can be set. The same level is set for both two

DMAC channels. When interrupts occur simultaneously, channel 0 has priority.

Bits 7 to 4—Watchdog Timer (WDT) Interrupt Priority Level 3 to 0 (WDTIP3–WDTIP0): These

bits set the watchdog timer (WDT) interrupt priority level and bus state controller (BSC) interrupt

priority level. There are four bits, so levels 0–15 can be set. When WDT and BSC interrupts occur

simultaneously, the WDT interrupt has priority.

Bits 3 to 0—Reserved: These bits are always read as 0. The write value should always be 0.

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