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SH7616 Datasheet(PDF) 188 Page - Renesas Technology Corp

Part # SH7616
Description  32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
PDF  935 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7616 Datasheet(HTML) 188 Page - Renesas Technology Corp

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Section 5 Interrupt Controller (INTC)
Rev. 2.00 Mar 09, 2006 page 162 of 906
REJ09B0292-0200
5.3.4
Interrupt Priority Level Setting Register D (IPRD)
Interrupt priority level setting register D (IPRD) is a 16-bit read/write register that sets the priority
levels (0–15) of on-chip peripheral module interrupts. IPRD is initialized to H'0000 by a reset. It is
not initialized in standby mode.
Bit:
15
14
13
12
11
10
9
8
TPU0IP3 TPU0IP2 TPU0IP1 TPU0IP0 TPU1IP3 TPU1IP2 TPU1IP1 TPU1IP0
Initial value:
00000000
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
76543210
TPU2IP3 TPU2IP2 TPU2IP1 TPU2IP0 SCF1IP3 SCF1IP2 SCF1IP1 SCF1IP0
Initial value:
00000000
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 to 4—16-Bit Timer Pulse Unit 0 to 2 (TPU0–TPU2) Interrupt Priority Level 3 to 0
(TPUnIP3–TPUnIP0, n = 0–2): These bits set the 16-bit timer pulse unit 0 to 2 (TPU0–TPU2)
interrupt priority levels. There are four bits for each interrupt, so the value can be set between 0
and 15.
Bits 3 to 0—Serial Communication Interface with FIFO 1 (SCIF1) Interrupt Priority Level 3 to 0
(SCF1IP3–SCF1IP0): These bits set the serial communication interface with FIFO 1 (SCIF1)
interrupt priority level. There are four bits, so the value can be set between 0 and 15.



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