SH7616 datasheet(190/935 Pages) RENESAS

190 / 935 page

Section 5 Interrupt Controller (INTC)

Rev. 2.00 Mar 09, 2006 page 164 of 906

REJ09B0292-0200

Table 5.5

Interrupt Request Sources and IPRA–IPRE

Bits 15 to 12

Bits 11 to 8

Bits 7 to 4

Bits 3 to 0

Interrupt priority level setting

Reserved

DMAC0,

DMAC1

WDT, REF

Reserved

Interrupt priority level setting

E-DMAC

FRT

Reserved

Interrupt priority level setting

IRQ0

IRQ1

IRQ2

IRQ3

Interrupt priority level setting

TPU0

TPU1

TPU2

SCIF1

Interrupt priority level setting

SCIF2

SIOF

SIO1

SIO2

As table 5.5 shows, between two and four on-chip peripheral modules are assigned to each

interrupt priority level setting register. Set the priority levels by setting the corresponding 4-bit

groups with values in the range of H'0 (0000) to H'F (1111). H'0 is interrupt priority level 0 (the

lowest); H'F is level 15 (the highest). When two on-chip peripheral modules are assigned to the

same bits (DMAC0 and DMAC1, or WDT and BSC refresh control unit), those two modules have

the same priority. A reset initializes IPRA–IPRE to H'0000. They are not initialized in standby

mode.

5.3.6

Vector Number Setting Register WDT (VCRWDT)

Vector number setting register WDT (VCRWDT) is a 16-bit read/write register that sets the WDT

interval interrupt and BSC compare match interrupt vector numbers (0–127). VCRWDT is

initialized to H'0000 by a reset. It is not initialized in standby mode.

Bit:

—

WITV6

WITV5

WITV4

WITV3

WITV2

WITV1

WITV0

Initial value:

00000000

R/W:

R/W

Bit:

76543210

—

BCMV6 BCMV5 BCMV4 BCMV3 BCMV2 BCMV1 BCMV0

Initial value:

00000000

R/W:

R/W

Bits 15 and 7—Reserved: These bits are always read as 0. The write value should always be 0.

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