SH7616 datasheet(320/935 Pages) RENESAS

320 / 935 page

Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 294 of 906

REJ09B0292-0200

A10

CKIO

CKE

CSn

RAS

CAS/OE

RD/

D15

DQMLU/

WE1

DQMLL/

WE0

CLK

CKE

RAS

CAS

I/O15

I/O0

DQMU

DQML

Chip

256 k

× 16-bit

synchronous

DRAM

Figure 7.21 Synchronous DRAM 16-bit Device Connection

7.5.2

Address Multiplexing

Addresses are multiplexed according to the MCR’s address multiplex specification bits AMX2–

AMX0 and size specification bit SZ so that synchronous DRAMs can be connected to the SH7616

directly without an external multiplex circuit

. Table 7.6 shows the relationship between the

multiplex specification bits and bit output to the address pins.

A24–A16 always output the original value regardless of multiplexing.

When SZ = 0, the data width on the synchronous DRAM side is 16 bits and the LSB of the

device’s address pins (A0) specifies word address. The A0 pin of the synchronous DRAM is thus

connected to the A1 pin of the SH7616, the rest of the connection proceeding in the same order,

beginning with the A1 pin to the A2 pin.

When SZ = 1, the data width on the synchronous DRAM side is 32 bits and the LSB of the

device’s address pins (A0) specifies longword address. The A0 pin of the synchronous DRAM is

thus connected to the A2 pin of the SH7616, the rest of the connection proceeding in the same

order, beginning with the A1 pin to the A3 pin.

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