SH7616 datasheet(322/935 Pages) RENESAS

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Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 296 of 906

REJ09B0292-0200

Setting

External Address Pins

SZ AMX2 AMX1 AMX0

Output

Timing

A1–A8

A10

A11

A12

A13

A14

A15

100

Column

address

A1–A8

A10

LH*

A12

A21*

3 A22*2 A15

Row

address

A9–A16 A17

A18

A19

A20

A21*

3 A22*2 A23

011

Column

address

A1–A8

L/H*

A18*

2 A11

A12

A13

A14

A15

Row

address

A9–A16 A17

A18*

2 A19

A20

A21

A22

A23

111

Column

address

A1–A8

L/H*

A17*

2 A11

A12

A13

A14

A15

Row

address

A9–A16 A16

A17*

2 A19

A20

A21

A22

A23

Notes: AMX2–AMX0 setting 110 is reserved and must not be used. When SZ = 0, AMX2–AMX0

settings 001, 010, and 101 are also reserved and must not be used.

1. L/H is a bit used to specify commands. It is fixed at L or H according to the access

mode.

2. Bank address specification.

3. Bank address specification when using four banks.

7.5.3

Burst Reads

Figure 7.22 (a) and (b) show the timing charts for burst reads. In the following example, 2

synchronous DRAMs of 256k

× 16 bits are connected, the data width is 32 bits and the burst

length is 4. After a Tr cycle that performs ACTV command output, a READA command is issued

in the Tc cycle, read data is accepted in cycles Td1 to Td4, and the end of the read sequence is

waited for in the Tde cycle. One Tde cycle is issued when I

φ : Eφ ≠ 1 : 1, and two cycles when Iφ

: E

φ = 1 : 1. Tap is a cycle for waiting for the completion of the auto-precharge based on the

READA command within the synchronous DRAM. During this period, no new access commands

are issued to the same bank. Accesses of the other bank of the synchronous DRAM by another CS

space are possible. Depending on the TRP1, TRP0 specification in MCR, the chip determines the

number of Tap cycles and does not issue a command to the same bank during that period.

Figure 7.22 (a) and (b) show examples of the basic cycle. Because a slower synchronous DRAM is

connected, setting WCR1 and MCR bits can extend the cycle. The number of cycles from the

ACTV command output cycle Tr to the READA command output cycle Tc can be specified by

bits RCD1 and RCD0 in MCR. 00 specifies 1 cycle, 01 specifies 2 cycles, and 10 specifies 3

cycles. For 2 or 3 cycles, a NOP command issue cycle Trw for the synchronous DRAM is inserted

between the Tr cycle and the Tc cycle. The number of cycles between the READA command

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