HD6433713 datasheet(147/324 Pages) RENESAS

147 / 324 page

8.1.1 Prescaler Operation

Prescaler S (PSS)

Prescaler S is a 13-bit counter using the system clock (

φ = f

OSC/2) as its input clock. Each

input clock cycle causes prescaler S to increment once.

Prescaler S is initialized to H'0000 by a reset, and starts counting upon return to active mode.

In standby mode, watch mode, and subactive mode, the system clock (

φ) pulse generator

stops, so prescaler S also stops functioning. Its value is reset to H'0000.

The CPU cannot read or write prescaler S data.

The output from prescaler S is shared by timers A to C and E as well as serial communication

interfaces 1 and 2. The frequency division ratio can be set separately for each on-chip

peripheral function.

Prescaler W (PSW)

Prescaler W is a 5-bit counter using the subclock (

SUB = fX/8) as its input clock.

Prescaler W is initialized to H'00 by a reset, and starts counting upon return to active mode.

Even in standby mode, watch mode, or subactive mode, prescaler W continues functioning so

long as clock signals are supplied to pins X1 and X2.

Prescaler W can be reset by setting bits TMA3 and TMA2 to 1 in timer mode register A

(TMA).

The output from prescaler W can be used as the clock source for timer A, in which case timer

A functions as a time base.

Figure 8-1 shows the clock signals supplied by prescalers S and W to peripheral modules.

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HD6433713 Datasheet(PDF) 147 Page - Renesas Technology Corp