HD6433713 datasheet(166/324 Pages) RENESAS

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Pin configuration

Table 8-7 shows the timer D pin configuration.

Table 8-7 Pin Configuration

Name

Abbrev.

I/O

Function

Event input pin

P16/EVENT

Input

Timer D event input

Table 8-8 shows the register configuration of timer D.

Table 8-8 Timer D Registers

Name

Abbrev.

R/W

Initial Value

Address

Timer mode register D

TMD

R/W*

H'7E

H'FFC6

Timer counter D

TCD

H'00

H'FFC7

Note: * Writing to bit 7 of TMD is possible only when writing 1 to clear the counter.

8.5.2 Register Descriptions

Timer mode register D (TMD)

TMD is an 8-bit read/write register for clearing timer counter D (TCD), and for selecting whether

input at the external event pin is sensed at the rising or falling edge.

Bit 7: Counter clear (CLR)

Bit 7 initializes TCD to H'00.

Bit 7

CLR

Description

After 1 is written to this bit to initialize TCD, it is cleared to 0 by

(initial value)

hardware.

Initializes TCD to H'00.

Bit

Initial value

Read/Write

CLR

—

EDG

R/W

—

155

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