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HD6433713 Datasheet(PDF) 167 Page - Renesas Technology Corp |
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HD6433713 Datasheet(HTML) 167 Page - Renesas Technology Corp |
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167 / 324 page  Bits 6 to 1: Reserved bits Bits 6 to 1 are reserved; they always read 1, and cannot be modified. Bit 0: Edge select (EDG) Bit 0 selects the rising or falling edge of input at external event pin P16/EVENT. Bit 0 EDG Description 0 TCD counts falling edges of input at pin P16/EVENT. (initial value) 1 TCD counts rising edges of input at pin P16/EVENT. 2. Timer counter D (TCD) TCD is an 8-bit read-only up-counter, which is incremented by external clock input at pin P16/EVENT. The input clock edge is selected by the EDG bit in timer mode register D (TMD). The TCD value can be read by the CPU at any time. When TCD overflows from H'FF to H'00, the IRRTD bit in interrupt request register 2 (IRR2) is set to 1. Upon reset, TCD is initialized to H'00. Bit Initial value Read/Write 7 TCD7 0 R 6 TCD6 0 R 5 TCD5 0 R 4 TCD4 0 R 3 TCD3 0 R 0 TCD0 0 R 2 TCD2 0 R 1 TCD1 0 R 156 |
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