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HD6433713 Datasheet(PDF) 168 Page - Renesas Technology Corp |
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HD6433713 Datasheet(HTML) 168 Page - Renesas Technology Corp |
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168 / 324 page  8.5.3 Timer Operation 1. Operation on external clock Timer D operates on an external clock input at pin P16/EVENT, used as an event input pin. The rising or falling edge of this input is selected by the EDG bit in timer mode register D (TMD). After the count value in TCD reaches H'FF, the next clock signal input causes timer D to overflow, setting bit IRRTD in interrupt request register 2 (IRR2) to 1 . If bit IENTD = 1 in interrupt enable register 2 (IENR2), a CPU interrupt is requested.* At overflow, TCD returns to H'00 and starts counting up again. TCD can be cleared by setting the CLR bit to 1 in TMD. To use external event input, the EVENT bit in port mode register 1 (PMR1) must be set to 1. Note: * For details on interrupts, see 3.2.2, Interrupts. 157 |
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