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HD6433713 Datasheet(PDF) 165 Page - Renesas Technology Corp |
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HD6433713 Datasheet(HTML) 165 Page - Renesas Technology Corp |
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165 / 324 page  8.5 Timer D 8.5.1 Overview Timer D is an 8-bit event counter, which is incremented by input of an external event signal. Either rising or falling edges of the external event signal can be counted. 1. Features Features of timer D are given below. • Choice of rising or falling edge for external event counting. • An interrupt is requested when the counter overflows. 2. Block diagram Figure 8-5 shows a block diagram of timer D. Figure 8-5 Block Diagram of Timer D TMD TCD EVENT IRRTD Notation: TMD: TCD: IRRTD: Timer mode register D Timer counter D Timer D overflow interrupt request flag (interrupt request register 2) 154 |
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