HD6433713 datasheet(162/324 Pages) RENESAS

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Bits 2 to 0 select the clock input to TCC. For external clock counting, either the rising or falling

edge can be selected.

Bit 2

Bit 1

Bit 0

TMC2

TMC1

TMC0

Description

Internal clock:

φ/8192.

(initial value)

Internal clock:

φ/2048.

Internal clock:

φ/512.

Internal clock:

φ/256.

Internal clock:

φ/128.

Internal clock:

φ/32.

Internal clock:

φ/8.

External clock (P11/IRQ1): rising or falling edge.*

Note: * The edge of the external clock is selected by bit IEG1 in the IRQ edge select register

(IEGR). For details see 3.2.3 2, IRQ edge select register (IEGR).

Timer counter C (TCC)

TCC is an 8-bit read-only up-/down-counter, which is incremented or decremented by internal or

external clock input. The clock source for input to this counter is selected by bits TMC2 to TMC0

in timer mode register C (TMC). The TCC value can be read by the CPU at any time.

When TCC overflows (from H'FF to H'00 or to the value set in TLC) or underflows (from H'00 to

H'FF or to the value set in TLC), the IRRTC bit in interrupt request register 2 (IRR2) is set to 1.

TCC is allocated to the same address as timer load register C (TLC).

Upon reset, TCC is initialized to H'00.

Bit

Initial value

Read/Write

TCC7

TCC6

TCC5

TCC4

TCC3

TCC0

TCC2

TCC1

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HD6433713 Datasheet(PDF) 162 Page - Renesas Technology Corp

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