HD6433713 datasheet(164/324 Pages) RENESAS

164 / 324 page

After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C

to overflow (underflow), setting bit IRRTC to 1 in interrupt request register 2 (IRR2). If bit

IENTC = 1 in interrupt enable register 2 (IENR2), a CPU interrupt is requested.*

At overflow or underflow, TCC returns to H'00 or H'FF and starts counting up or down again.

During interval timer operation (TMC7 = 0), when a value is set in timer load register C

(TLC), the same value is set in TCC.

Note: * For details on interrupts, see 3.2.2, Interrupts.

•

Auto-reload timer operation

Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When

a reload value is set in TLC, the same value is loaded into TCC, becoming the value from

which TCC starts its count.

After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C

to overflow (or underflow). The TLC value is then loaded into TCC, and the count continues

from that value. The overflow (underflow) period can be set within a range from 1 to 256

input clocks, depending on the TLC value.

The clock sources, up/down control, and interrupts in auto-reload mode are the same as for

interval mode.

In auto-reload mode (bit TMC7 = 1), setting a new TLC value also initializes TCC.

Operation on external clock

Timer C can operate on an external clock input as an event signal at pin P11/IRQ1. External

clock operation is selected by setting bits TMC2 to TMC0 in timer mode register C to all 1’s

(111). TCC can count either rising or falling edges of the input at pin P11/IRQ1.

When timer C is used to count external event input, bit IRQC1 in port mode register 1

(PMR1) should be set to 1, and bit IEN1 in interrupt enable register 1 (IENR1) should be

cleared to 0 to disable IRQ1 interrupt requests.

TCC up/down control by hardware

The counting direction of timer C can be controlled by input at pin P97/UD. When bit TMC6

in TMC is set to 1, high-level input at the UD pin selects down-counting, while low-level

input selects up-counting.

When using input at pin UD for this control function, set the UP/DOWN bit in port mode

153

HD6433713 Datasheet(PDF) 164 Page - Renesas Technology Corp