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DS26521 Datasheet(PDF) 65 Page - Maxim Integrated Products |
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DS26521 Datasheet(HTML) 65 Page - Maxim Integrated Products |
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65 / 258 page  DS26521 Single T1/E1/J1 Transceiver 65 of 258 8.10.2 Transmit HDLC Controller 8.10.2.1 FIFO Information The Transmit HDLC FIFO Buffer Available register (TFBA) indicates the number of bytes that can be written into the transmit FIFO. The count from this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer. This is a real-time register. The count shall remain valid and stable during the read cycle. 8.10.2.2 HDLC Transmit Example The HDLC status registers in the DS26521 allow for flexible software interface to meet the user’s preferences. When transmitting HDLC messages, the host can choose to be interrupt driven, or to poll to desired status registers, or a combination of polling and interrupt processes can be used. An example routine for using the DS26521 HDLC receiver is given in Figure 8-16. |
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