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DS26521 Datasheet(PDF) 44 Page - Maxim Integrated Products |
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DS26521 Datasheet(HTML) 44 Page - Maxim Integrated Products |
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44 / 258 page ![]() DS26521 Single T1/E1/J1 Transceiver 44 of 258 8.9.4 Signaling The DS26521 supports both software- and hardware-based signaling. Interrupts can be generated on changes of signaling data. The DS26521 is also equipped with receive-signaling freeze on loss of synchronization (OOF), carrier loss, or change of frame alignment. The DS26521 also has hardware pins to indicate signaling freeze. • Flexible signaling support o Software or hardware based o Interrupt generated on change of signaling data o Receive-signaling freeze on loss of frame, loss of signal, or change of frame alignment • Hardware pins for carrier loss and signaling freeze indication Table 8-11. Registers Related to Signaling REGISTER FRAMER ADDRESSES FUNCTION Transmit-Signaling Registers 1 to 16 (TS1 to TS16) 140h to 14Bh (T1/J1) 140h to 14Fh (E1 CAS) Transmit ABCD signaling. Software-Signaling Insertion Enable Registers 1 to 4 (SSIE1 to SSIE4) 118h, 119h, 11Ah, 11Bh When enabled, signaling is inserted for the channel. Transmit Hardware-Signaling Channel Select Registers 1 to 4 (THSCS1 to THSCS4) 1C8h, 1C9h, 1CAh, 1CBh Bits determine which channels will have signaling inserted in hardware-signaling mode. Receive-Signaling Control Register (RSIGC) 013h Freeze control for receive signaling. Receive-Signaling All-Ones Insertion Registers 1 to 3 (T1RSAOI1 to T1RSAOI3) 038h, 039h, 03Ah Registers for all-ones insertion (T1 mode only). Receive-Signaling Registers 1 to 16 (RS1 to RS16) 040h to 04Bh (T1/J1) 040h to 04Fh (E1) Receive-signaling bytes. Receive-Signaling Status Registers 1 to 4 (RSS1 to RSS4) 098h to 09Ah (T1/J1) 98h to 9Fh (E1) Receive-signaling change of status bits. Receive-Signaling Change of State Enable Registers 1 to 4 (RSCSE1 to RSCSE4) 0A8h, 0A9h, 0AAh, 0ABh Receive-signaling change of state interrupt enable. Receive Latched Status Register 4 (RLS4) 093h Receive-signaling change of state bit. Receive Interrupt Mask Register 4 (RIM4) 0A3h Receive-signaling change of state interrupt mask bit. Receive-Signaling Reinsertion Enable Registers 1 to 4 (RSI1 to RSI4) 0C8h, 0C9h, 0CAh, 0CBh Registers for signaling reinsertion. |
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