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DS26521 Datasheet(PDF) 31 Page - Maxim Integrated Products

Part # DS26521
Description  Single T1/E1/J1 Transceiver
PDF  258 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

DS26521 Datasheet(HTML) 31 Page - Maxim Integrated Products

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DS26521 Single T1/E1/J1 Transceiver
31 of 258
Figure 8-10. Device Interrupt Information Flow Diagram
Receive Remote Alarm Indication Clear
7
Receive Alarm Condition Clear
6
Receive Loss of Signal Clear
5
Receive Loss of Frame Clear
4
Receive Remote Alarm Indication
3
Receive Alarm Condition
2
Receive Loss of Signal
1
Receive Loss of Frame
0
Receive Signal All Ones
3
Receive Signal All Zeros
2
Receive CRC-4 Multiframe
1
Receive Align Frame
0
Loss of Receive Clock Clear/Loss of Receive Clock Clear
7
Spare Code Detected Condition Clear
6
Loop Down Code Clear/V52 Link Clear
5
Loop Up Code Clear/Receive Distant MF Alarm Clear
4
Loss of Receive Clock/Loss of Receive Clock
3
Spare Code Detect
2
Loop Down Detect/V52 Link Detect
1
Loop Up Detect/Receive Distant MF Alarm Detect
0
Receive Elastic Store Full
7
Receive Elastic Store Empty
6
Receive Elastic Store Slip
5
Receive Signaling Change of State (Enable in RSCSE1:4)
3
One-Second Timer
2
Timer
1
Receive Multiframe
0
Receive FIFO Overrun
5
Receive HDLC Opening Byte
4
Receive Packet End
3
Receive Packet Start
2
Receive Packet High Watermark
1
Receive FIFO Not Empty
0
Receive RAI-CI
5
Receive AIS-CI
4
Receive SLC-96 Alignment
3
Receive FDL Register Full
2
Receive BOC Clear
1
Receive BOC
0
Transmit Elastic Store Full
7
Transmit Elastic Store Empty
6
Transmit Elastic Store Slip
5
Transmit SLC-96 Multiframe
4
Transmit Pulse Density Violation/Transmit Align Frame
3
Transmit Multiframe
2
Loss of Transmit Clock Clear
1
Loss of Transmit Clock
0
Transmit FDL Register Empty
4
Transmit FIFO Underrun
3
Transmit Message End
2
Transmit FIFO Below Low Watermark
1
Transmit FIFO Not Full Set
0
—
-
—
-
Loss of Frame
1
Loss of Frame Synchronization
0
Jitter Attenuator Limit Trip Clear
7
Open-Circuit Detect Clear
6
ShortCircuit Detect Clear
5
Loss of Signal Detect Clear
4
Jitter Attenuator Limit Trip
3
Open-Circuit Detect
2
Short-Circuit Detect
1
Loss of Signal Detect
0
BERT Bit-Error Detected
6
BERT Bit Counter Overflow
5
BERT Error Counter Overflow
4
BERT Receive All Ones
3
BERT Receive All Zeros
2
BERT Receive Loss of Synchronization
1
BERT in Synchronization
0
0
1
2
3
4
5
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DRAWING LEGEND:
INTERRUPT
STATUS
REGISTERS
REGISTER NAME
INTERRUPT MASK
REGISTERS
REGISTER NAME



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