DS26521 datasheet(22/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

22 of 258

NAME

TYPE

FUNCTION

RCHBLK/

CLK

Receive Channel Block/Receive Channel Block Clock.

This pin can be

configured to output either RCHBLK or RCHCLK. RCHBLK is a user-

programmable output that can be forced high or low during any of the 24 T1 or 32

E1 channels. It is synchronous with RCLK when the receive-side elastic store is

disabled. It is synchronous with RSYSCLK when the receive-side elastic store is

enabled. This pin is useful for blocking clocks to a serial UART or LAPD controller

in applications where not all channels are used such as fractional service, 384kbps

service, 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-

and-insert applications, for external per-channel loopback, and for per-channel

conditioning.

RCHCLK.

RCHCLK is a 192kHz (T1) or 256kHz (E1) clock that pulses high during

the LSB of each channel. It is synchronous with RCLK when the receive-side

elastic store is disabled. It is synchronous with RSYSCLK when the receive-side

elastic store is enabled. It is useful for parallel-to-serial conversion of channel data.

BPCLK

Backplane Clock.

Programmable clock output that can be set to 2.048MHz,

4.096MHz, 8.192MHz, or 16.384MHz. The reference for this clock can be RCLK

from any of the LIU, 1.544MHz, or 2.048MHz frequency derived from MCLK or an

external reference clock. This allows for the IBO clock to reference from an

external source or the T1/J1/E1 recovered clock or the MCLK oscillator.

MICROPROCESSOR INTERFACE

A12

Address [12], [8:0].

This bus selects a specific register in the DS26521 during

read/write access. A12 is the MSB and A0 is the LSB. Note: A9, A10, and A11 are

internally pulled low. Connect device A12 to microprocessor A12 to ensure

software compatibility with other TEX-series transceivers. See Section 9 for further

information.

D[7]/

SPI_CPOL

Data [7]/SPI Interface Clock Polarity

D[7]: Bit 7 of the 16-bit or 8-bit data bus used to input data during register writes

and data outputs during register reads. Not driven when

CS = 1.

SPI_CPOL:

This signal selects the clock polarity when SPI_SEL = 1. See Section

8.1.3 for detailed timing and functionality information. Default setting is low.

D[6]/

SPI_CPHA

Data [6]/SPI Interface Clock Phase

D[6]: Bit 6 of the 16-bit or 8-bit data bus used to input data during register writes,

and data outputs during register reads. Not driven when

CS = 1.

SPI_CPHA:

This signal selects the clock phase when SPI_SEL = 1. See Section

8.1.3 for detailed timing and functionality information. Default setting is low.

D[5]/

SPI_SWAP

Data [5]/SPI Bit Order Swap

D[5]: Bit 5 of the 16-bit or 8-bit data bus used to input data during register writes,

and data outputs during register reads. Not driven when

CSB = 1.

SPI_SWAP:

This signal is active when SPI_SEL = 1. The address and data bit

order is swapped when SPI_SWAP is high. The R/W and B bit positions are never

changed in the control word.

0 = LSB is transmitted and received first.

1 = MSB is transmitted and received first.

D[4]

Data [4].

Bit 4 of the 8-bit data bus used to input data during register writes, and

data outputs during register reads. Not driven when

CSB = 1.

D[3]

Data [3].

Bit 3 of the 8-bit data bus used to input data during register writes, and

data outputs during register reads. Not driven when

CSB = 1.

DS26521 Datasheet(PDF) 22 Page - Maxim Integrated Products

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