DS26521 datasheet(79/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

79 of 258

8.12

Bit-Error-Rate Test (BERT) Function

The bit-error-rate tester (BERT) block can generate and detect both pseudorandom and repeating bit patterns. It is

used to test and stress data-communication links. BERT functionality is dedicated for each of the transceivers.

Table 8-35 shows the registers related to the configure, control, and status of the BERT.

Table 8-35. Registers Related to BERT Configure, Control, and Status

FRAMER

ADDRESSES

FUNCTION

Global BERT Interrupt Status Register

(GBISR)

0FAh

When the BERT issues an interrupt, a bit is

set.

Global BERT Interrupt Mask Register

(GBIMR)

0FDh

When the BERT issues an interrupt, a bit is

set.

Receive Expansion Port Control Register

(RXPC)

08Ah

Enable for the receiver BERT.

Receive BERT Port Bit Suppress Register

(RBPBS)

08Bh

Bit suppression for the receive BERT.

Receive BERT Port Channel Select

Registers 1 to 4 (RBPCS1:RBPCS4)

0D4h, 0D5h, 0D6h,

0D7h

Channels to be enabled for the framer to

accept data from the BERT pattern generator.

Transmit Expansion Port Control Register

(TXPC)

18Ah

Enable for the transmitter BERT

Transmit BERT Port Bit Suppress

18Bh

Bit suppression for the transmit BERT

Transmit BERT Port Channel Select

Registers 1 to 4 (TBPCS1:TBPCS4)

1D4h, 1D5h, 1D6h,

1D7h

Channels to be enabled for the framer to

accept data from the transmit BERT pattern

generator.

BERT Alternating Word Count Rate

1100h

BERT alternating pattern count register.

BERT Repetitive Pattern Set Register 1

(BRP1)

1101h

BERT repetitive pattern set register 1.

BERT Repetitive Pattern Set Register 2

(BRP2)

1102h

BERT repetitive pattern set register 2.

BERT Repetitive Pattern Set Register 3

(BRP3)

1103h

BERT repetitive pattern set register 3.

BERT Repetitive Pattern Set Register 4

(BRP4)

1104h

BERT repetitive pattern set register 4.

BERT Control Register 1 (BC1)

1105h

Pattern selection and miscellaneous control.

BERT Control Register 2 (BC2)

1106h

BERT bit pattern length control.

BERT Bit Count Register 1 (BBC1)

1107h

BERT bit counter—increments for BERT bit

clocks.

BERT Bit Count Register 2 (BBC2)

1108h

BERT bit counter.

BERT Bit Count Register 3 (BBC3)

1109h

BERT bit counter.

BERT Bit Count Register 4 (BBC4)

110Ah

BERT bit counter.

BERT Error Count Register 1 (BEC1)

110Bh

BERT error counter.

BERT Error Count Register 2 (BEC2)

110Ch

BERT error counter.

BERT Error Count Register 3 (BEC3)

110Dh

BERT error counter.

BERT Latched Status Register (BLSR)

110Eh

BERT status registers—denotes

synchronization loss and other status.

BERT Status Interrupt Mask Register

(BSIM)

110Fh

BERT Interrupt mask.

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