DS26521 datasheet(80/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

80 of 258

The BERT block can generate and detect the following patterns:

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The pseudorandom patterns 2E7-1, 2E9-1, 2E11-1, 2E15-1, and QRSS

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A repetitive pattern from 1 to 32 bits in length

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Alternating (16-bit) words that flip every 1 to 256 words

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Daly pattern

The BERT function must be enabled and configured in the TXPC and RXPC registers for each port. The BERT can

then be assigned on a per-channel basis for both the transmitter and receiver, using the special per-channel

function in the TBPCS1:TBPCS4 and RBCS1:RBCS4 registers. Individual bit positions within the channels can be

suppressed with the TBPBS and RBPBS registers. Using combinations of these functions, the BERT pattern can

be transmitted and/or received in single or across multiple DS0s, contiguous or broken. Transmit and receive

bandwidth assignments are independent of each other.

The BERT receiver has a 32-bit bit counter and a 24-bit error counter. The BERT receiver can generate interrupts

on: a change in receive-synchronizer status, receive all zeros, receive all ones, error counter overflow, bit counter

overflow, and bit error detection. Interrupts from each of these events can be masked within the BERT function via

the BERT Status Interrupt Mask register (BSIM). If the software detects that the BERT has reported an event, then

the software must read the BERT Latched Status register (BLSR) to determine which event(s) has occurred.

8.12.1 BERT Repetitive Pattern Set

These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a

pseudorandom pattern, alternating word pattern, or a Daly pattern. For a repetitive pattern that is fewer than 32

bits, the pattern should be repeated so that all 32 bits are used to describe the pattern. For example, if the pattern

was the repeating 5-bit pattern …01101… (where the rightmost bit is the one sent first and received first), then

BRP1 should be loaded with ADh, BRP2 with B5h, BRP3 with D6h, and BRP4 should be loaded with 5Ah. For a

pseudorandom pattern, all four registers should be loaded with all ones (i.e., FFh). For an alternating word pattern,

one word should be placed into BRP1 and BRP2 and the other word should be placed into BRP3 and BRP4. For

example, if the DDS stress pattern “7E” is to be described, the user would place 00h in BRP1, 00h in BRP2, 7Eh in

BRP3, and 7Eh in BRP4, and the alternating word counter would be set to 50 (decimal) to allow 100 bytes of 00h

followed by 100 bytes of 7Eh to be sent and received.

8.12.2 BERT Error Counter

Once the BERT has achieved synchronization, this 24-bit counter will increment for each data bit received in error.

Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and will set the BECO

status bit in the BLSR register.

DS26521 Datasheet(PDF) 80 Page - Maxim Integrated Products