DS26521 datasheet(38/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

38 of 258

8.9

Framers

The DS26521 framer core is software selectable for T1, J1, or E1. The receive framer locates the frame and

multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling

data, T1 FDL data, and E1 Si- and Sa-bit information. The receive-side framer decodes AMI, B8ZS line coding,

synchronizes to the data stream, reports alarm information, counts framing/coding and CRC errors, and provides

clock/data and frame-sync signals to the backplane interface section. Diagnostic capabilities include loopbacks,

and 16-bit loop-up and loop-down code detection. The device contains a set of internal registers for host access

and control of the device.

On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface

section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and

inserts the CRC codes, and provides the B8ZS (zero code suppression) and AMI line coding.

Both the transmit and receive path have an HDLC controller. The HDLC controller transmits and receives data via

the framer block. The HDLC controller can be assigned to any time slot, portion of a time slot, or to FDL (T1). The

HDLC controller has separate 64-byte Tx and Rx FIFO to reduce the amount of processor overhead required to

manage the flow of data.

The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic

stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz,

4.096MHz, 8.192MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions

(asynchronous interface). An IBO is provided to allow multiple framers in the DS26521 to share a high-speed

backplane.

8.9.1

T1 Framing

DS1 trunks contain 24 bytes of serial voice/data channels bundled with an overhead bit, the F-bit. The F-bit

contains a fixed pattern for the receiver to delineate the frame boundaries. The F-bit is inserted once per frame at

the beginning of the transmit frame boundary. The frames are further grouped into bundles of frames 12 for D4 and

24 for ESF.

The D4 and ESF framing modes are outlined in Table 8-5 and Table 8-6. In the D4 mode, framing bit for frame 12

is ignored if Japanese Yellow is selected.

Table 8-5. D4 Framing Mode

FRAME

NUMBER

SIGNALING

DS26521 Datasheet(PDF) 38 Page - Maxim Integrated Products