DS26521 datasheet(60/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

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8.9.16 T1 Programmable In-Band Loop Code Detection

The DS26521 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This

function is available only in T1 mode.

Table 8-26. Registers Related to T1 In-Band Loop Code Detection

FRAMER

ADDRESSES

FUNCTION

Receive In-Band Code Control Register

(T1RIBCC)

082h

Used for selecting length of receive in-

band loop code register.

Receive Up Code Definition Register 1

(T1RUPCD1)

0ACh

Receive up code definition register 1.

Receive Up Code Definition Register 2

(T1RUPCD2)

0ADh

Receive up code definition register 2.

Receive Down Code Definition Register 1

(T1RDNCD1)

0AEh

Receive down code definition register 1.

Receive Down Code Definition Register 2

(T1RDNCD2)

0AFh

Receive up code definition register 2.

Receive Spare Code Register 1 (T1RSCD1)

09Ch

Receive spare code register 1.

Receive Spare Code Register 2 (T1RSCD2)

09Dh

Receive spare code register 2.

Receive Real-Time Status Register 3 (RRTS3)

0B2h

Real-time loop code detect.

Receive Latched Status Register 3 (RLS3)

092h

Latched loop code detect bits.

Receive Interrupt Mask Register 3 (RIM3)

0A2h

Mask for latched loop code detect bits.

The framer has three programmable pattern detectors. Typically, two of the detectors are used for “loop-up” and

“loop-down” code detection. The user programs the codes to be detected in the Receive Up Code Definition

registers (T1RUPCD1 and T1RUPCD2) and the Receive Down Code Definition registers (T1RDNCD1 and

T1RDNCD2). The length of each pattern is selected via the Receive In-Band Code Control register (T1RIBCC).

There is a third detector (Spare) and it is defined and controlled via the T1RSCD1/T1RSCD2 and T1RSCC

registers. When detecting a 16-bit pattern, both receive code definition registers are used together to form a 16-bit

2-, 3-, 4-, 5-, 6-, and 7-bit pattern only requires the first receive code definition register to be filled. The framer

detects repeating pattern codes in both framed and unframed circumstances with bit-error rates as high as 10E-2.

The detectors can handle both F-bit inserted and F-bit overwrite patterns. Writing the least significant byte of the

receive code definition register resets the integration period for that detector. The code detector has a nominal

integration period of 48ms. Thus, after about 48ms of receiving a valid code, the proper status bit (LUP, LDN, and

LSP) is set to 1. Note that real-time status bits, as well as latched set and clear bits, are available for LUP, LDN,

and LSP (RRTS3 and RLS3). Normally codes are sent for a period of 5 seconds. It is recommended that the

software poll the framer every 50ms to 100ms until 5 seconds has elapsed to ensure that the code is continuously

present.

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