DS26521 datasheet(36/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

36 of 258

8.8.3

H.100 (CT Bus) Compatibility

The registers used for controlling the H.100 backplane are RIOCR and TIOCR.

The H.100 (or CT bus) is a synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard

also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit H100EN

(RIOCR.5), when combined with RSYNCINV and TSSYNCINV, allows the DS26521 to accept a CT bus-

compatible frame-sync signal (

CT_FRAME) at the RSYNC and TSSYNCIO (input mode) inputs.

The following rules apply to the H100EN control bit.

1) The H100EN bit controls the sampling point for the RSYNC (input mode) and TSSYNCIO (input mode)

only. The RSYNC output and other sync signals are not affected.

2) The H100EN bit would always be used in conjunction with the receive and transmit elastic store buffers.

3) The H100EN bit would typically be used with 8.192MHz IBO mode, but could also be used with 4.096MHz

IBO mode or 2.048MHz backplane operation.

4) The H100EN bit in RIOCR controls both RSYNC and TSSYNCIO (i.e., there is no separate control bit for

the TSSYNCIO).

5) The H100EN bit does not invert the expected signal; RSYNCINV (RIOCR) and TSSYNCINV (TIOCR) must

be set high to invert the inbound sync signals.

Figure 8-12. RSYNC Input in H.100 (CT Bus) Mode

BIT 8

BIT 1

BIT 2

RSYNC

RSYSCLK

RSER

tBC

NOTE 1: RSYNC INPUT MODE IN NORMAL OPERATION.

NOTE 2: RSYNC INPUT MODE, H.100EN = 1 AND RSYNCINV = 1.

NOTE 3: tBC (BIT CELL TIME) = 122ns (typ). tBC = 244ns or 488ns ALSO ACCEPTABLE.

DS26521 Datasheet(PDF) 36 Page - Maxim Integrated Products