DS26521 datasheet(12/258 Pages) MAXIM

12 / 258 page

DS26521 Single T1/E1/J1 Transceiver

12 of 258

2.7

HDLC Controllers

One HDLC controller engine for each T1/E1 port

Independent 64-byte Rx and Tx buffers with interrupt support

Access FDL, Sa, or single DS0 channel

Compatible with polled or interrupt driven environments

2.8

Test and Diagnostics

IEEE 1149.1 support

Per-channel programmable on-chip bit error-rate testing (BERT)

Pseudorandom patterns including QRSS

User-defined repetitive patterns

Daly pattern

Error insertion single and continuous

Total-bit and errored-bit counts

Payload error insertion

Error insertion in the payload portion of the T1 frame in the transmit path

Errors can be inserted over the entire frame or selected channels

Insertion options include continuous and absolute number with selectable insertion rates

F-bit corruption for line testing

Loopbacks (remote, local, analog, and per-channel loopback)

2.9

Microcontroller Parallel Port

8-bit parallel control port

Intel or Motorola nonmultiplexed support

Flexible status registers support polled, interrupt, or hybrid program environments

Software reset supported

Hardware reset pin

Software access to device ID and silicon revision

2.10

Slave Serial Peripheral Interface (SPI) Features

Software access to device ID and silicon revision

3-wire synchronous serial data link operating in full duplex slave mode up to 10Mbps

Glueless connection and fully compliant to Motorola popular communication processors such as MPC8260

and microcontrollers such as M68HC11

Software provision ability for active phase of the serial clock (i.e., rising edge vs. falling edge), bit ordering

of the serial data (most significant first versus least significant bit first)

Flexible status registers support polled, interrupt, or hybrid program environments

DS26521 Datasheet(PDF) 12 Page - Maxim Integrated Products