DS26521 datasheet(37/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

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Figure 8-13. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode

8.8.4

Receive and Transmit Channel Blocking Registers

The Receive Channel Blocking registers (RCBR1:RCBR4) and the Transmit Channel Blocking registers

(TCBR1:TCBR4) control the RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHBLK pins are user-

programmable outputs that can be forced either high or low during individual channels. These outputs can be used

to block clocks to a USART or LAPD controller in ISDN-PRI applications. When the appropriate bits are set to 1,

the RCHBLK and TCHBLK pins are held high during the entire corresponding channel time. When used with a T1

(1.544MHz) backplane, only TCBR1:TCBR2:TCBR3 are used. TCBR4 is included to support an E1 (2.048MHz)

backplane when the elastic store is configured for T1-to-E1 rate conversion. See Section 8.8.1.

8.8.5

Transmit Fractional Support (Gapped Clock Mode)

The DS26521 can be programmed to output gapped clocks for selected channels in the receive and transmit paths

to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN-PRI applications. When the

gapped clock feature is enabled, a gated clock is output on the TCHCLK signal. The channel selection is controlled

via the Transmit Gapped-Clock Channel Select registers (TGCCS1:TGCCS4). The transmit path is enabled for

gapped clock mode with the TGCLKEN bit (TESCR.6). Both 56kbps and 64kbps channel formats are supported as

determined by TESCR.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the

channel is omitted (only the seven most significant bits of the channel have clocks).

8.8.6

Receive Fractional Support (Gapped Clock Mode)

The DS26521 can be programmed to output gapped clocks for selected channels in the receive and transmit paths

to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN-PRI applications. When the

gapped clock feature is enabled, a gated clock is output on the RCHCLK signal. The channel selection is controlled

via the Receive Gapped-Clock Channel Select registers (RGCCS1:RGCCS4). The receive path is enabled for

gapped clock mode with the RGCLKEN bit (RESCR.6). Both 56kbps and 64kbps channel formats are supported as

determined by RESCR.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the

channel is omitted (only the seven most significant bits of the channel have clocks).

BIT 8

BIT 1

BIT 2

TSSYNCIO

TSYSCLK

TSER

tBC

NOTE 1: TSSYNCIO IN NORMAL OPERATION.

NOTE 2: TSSYNCIO WITH H.100EN = 1 and TSSYNCINV = 1.

NOTE 3: tBC (BIT CELL TIME) = 122ns (typ). tBC = 244ns OR 488ns ALSO ACCEPTABLE.

DS26521 Datasheet(PDF) 37 Page - Maxim Integrated Products