DS26521 datasheet(20/258 Pages) MAXIM

20 / 258 page

DS26521 Single T1/E1/J1 Transceiver

20 of 258

NAME

TYPE

FUNCTION

TSYNC

I/O

Transmit Synchronization.

A pulse at this pin establishes either frame or

multiframe boundaries for the transmit side. This signal can also be programmed to

output either a frame or multiframe pulse. If this pin is set to output pulses at frame

boundaries, it can also be set to output double-wide pulses at signaling frames in

T1 mode. The operation of this signals is synchronous with TCLK.

TSSYNCIO

I/O

Transmit System Synchronization In.

Only used when the transmit-side elastic

store is enabled. A pulse at this pin establishes either frame or multiframe

boundaries for the transmit side. Note that if the elastic store is enabled, frame or

multiframe boundary will be established for the transmitter. Should be tied low in

applications that do not use the transmit-side elastic store. The operation of this

signal is synchronous with TSYSCLK.

Transmit System Synchronization Out.

If configured as an output, an 8kHz

pulse synchronous to the BPCLK will be generated. This pulse in combination with

BPCLK can be used as an IBO master. The BPCLK can be sourced to RSYSCLK,

TSYSCLK, and TSSYNCIO as a source to RSYNC, and TSSYNCIO of DS26521

or RSYNC and TSSYNC of other Dallas Semiconductor parts.

TSIG

Transmit Signaling.

When enabled, this input samples signaling bits for insertion

into outgoing PCM data stream. Sampled on the falling edge of TCLK when the

transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK

when the transmit-side elastic store is enabled.

TCHBLK/

CLK

Transmit Channel Block/Transmit Channel Block Clock.

A dual function pin.

TCHBLK is a user-programmable output that can be forced high or low. It is

synchronous with TCLK when the transmit-side elastic store is disabled. It is

synchronous with TSYSCLK when the transmit-side elastic store is enabled. It is

useful for blocking clocks to a serial UART or LAPD controller in applications

where not all channels are used such as Fractional T1, Fractional E1, 384kbps

(H0), 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-

and-insert applications, for external per-channel loopback, and for per-channel

conditioning.

TCHCLK.

TCHCLK is a 192kHz (T1) or 256kHz (E1) clock that pulses high during

the LSB of the channel. It can also be programmed to output a gated transmit bit

clock controlled by TCHBLK. It is synchronous with TCLK when the transmit-side

elastic store is disabled. It is synchronous with TSYSCLK when the transmit-side

elastic store is enabled. Useful for parallel-to-serial conversion of channel data.

DS26521 Datasheet(PDF) 20 Page - Maxim Integrated Products

DS26521 Datasheet(HTML) 20 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL