DS26521 datasheet(73/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

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8.11.3 Receiver

The DS26521 contains identical receivers. Both receivers are designed to be fully software-selectable for E1, T1,

and J1 without the need to change any external resistors. The device couples to the receive E1 or T1 twisted pair

(or coaxial cable in 75

Ω E1 applications) via a 1:1 or 2:1 transformer. See Table 8-32 for transformer details.

Receive termination and sensitivity are user configurable. Receive termination is configurable for 75

Ω, 100Ω,

110

Ω, or 120Ω termination by setting the appropriate RIMPM[1:0] bits (LRISMR). When using the internal

termination feature, the resistors labeled Rr in Figure 8-17 should be 60

Ω each. If external termination is required,

the resistors need to be 37.5

Ω, 50Ω, or 60Ω each depending on the line impedance. Receive sensitivity is

configurable by setting the appropriate RSMS[1:0] bits (LRISMR).

The DS26521 uses a digital clock recovery system. The resultant E1, T1, or J1 clock derived from MCLK is

multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system uses the

clock from the PLL circuit to form a 16 times oversampler, which is used to recover the clock and data. This

oversampling technique offers outstanding performance to meet jitter tolerance specifications shown in

Figure 8-21.

Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1 AMI/B8ZS

waveform presented at the RTIP and RRING inputs. If the jitter attenuator (LTRCR) is placed in the receive path

(as is the case in most applications), the jitter attenuator restores the RCLK to an approximate 50% duty cycle. If

the jitter attenuator is either placed in the transmit path or is disabled, the RCLK output can exhibit slightly shorter

high cycles of the clock. This is due to the highly oversampled digital clock recovery circuitry. See Table 12-3 for

more details. When no signal is present at RTIP and RRING, a receive carrier loss (RCL) condition occurs and the

RCLK is derived from the JACLK source.

8.11.3.1

Receive Level Indicator

The DS26521 reports the signal strength at RTIP and RRING in approximately 2.5dB increments via RSL3:RSL0

located in the LIU Receive Signal Level register (LRSL). This feature is helpful when trouble shooting line

performance problems.

8.11.3.2

Receive G.703 Section 10 Synchronization Signal

The DS26521 can receive a 2.048MHz square-wave synchronization clock as specified in Section 10 of ITU-T

G.703. To use this mode, set the receive G.703 clock-enable bit RG703 (LRISMR.7) found in the LIU Receive

Impedance and Sensitivity Monitor register (LRISMR).

8.11.3.3

Receiver Monitor Mode

The receive equalizer is equipped with a monitor mode function that is used to overcome the signal attenuation

caused by the resistive bridge used in monitoring applications. This function allows for a resistive gain of up to

32dB, along with cable attenuation of 12dB to 30dB as shown in the LIU Receive Impedance and Sensitivity

Monitor register (LRISMR).

DS26521 Datasheet(PDF) 73 Page - Maxim Integrated Products

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