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DS26521 Datasheet(PDF) 11 Page - Maxim Integrated Products |
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DS26521 Datasheet(HTML) 11 Page - Maxim Integrated Products |
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11 / 258 page  DS26521 Single T1/E1/J1 Transceiver 11 of 258 Detailed alarm and status reporting with optional interrupt support Large path and line error counters − T1: BPV, CV, CRC-6, and framing bit errors − E1: BPV, CV, CRC-4, E-bit, and frame alignment errors − Timed or manual update modes DS1 Idle Code Generation on a per-channel basis in both transmit and receive paths − User defined − Digital Milliwatt ANSI T1.403-1999 support G.965 V5.2 link detect Ability to monitor one DS0 channel in both the transmit and receive paths In-band repeating pattern generators and detectors − Three independent generators and detectors − Patterns from 1 to 8 bits or 16 bits in length Bit-oriented code (BOC) support Flexible signaling support − Software or hardware based − Interrupt generated on change of signaling data − Optional receive-signaling freeze on loss of frame, loss of signal, or frame slip − Hardware pins provided to indicate loss of frame (LOF), loss of signal (LOS), loss of transmit clock (LOTC), or signaling freeze condition Automatic RAI generation to ETS 300 011 specifications RAI-CI and AIS-CI support Expanded access to Sa and Si bits Option to extend carrier loss criteria to a 1ms period as per ETS 300 233 Japanese J1 support Ability to calculate and check CRC-6 according to the Japanese standard Ability to generate Yellow Alarm according to the Japanese standard T1-to-E1 conversion 2.6 System Interface Independent two-frame receive and transmit elastic stores Independent control and clocking Controlled slip capability with status Minimum delay mode supported Flexible TDM backplane supports bus rates from 1.544MHz to 16.384MHz Supports T1 to CEPT (E1) conversion Programmable output clocks for fractional T1, E1, H0, and H12 applications Interleaving PCM bus operation Hardware signaling capability Receive-signaling reinsertion to a backplane multiframe sync Availability of signaling in a separate PCM data stream Signaling freezing Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode User-selectable synthesized clock output |
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