| Electronic Components Datasheet Search |
|
33903 Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
33903 Datasheet(HTML) 29 Page - Freescale Semiconductor, Inc |
|
29 / 104 page ![]() Analog Integrated Circuit Device Data Freescale Semiconductor 29 33903/4/5 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION BUS LOAD RBUS AND CBUS 1.0 NF / 1.0 KΩ, 6.8 NF / 660 Ω, 10 NF / 500 Ω. SEE Figure 20, PAGE 31. Duty Cycle 1: THREC(MAX) = 0.744 * VSUP THDOM(MAX) = 0.581 * VSUP D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V ≤ VSUP ≤ 18 V D1 0.396 - - Duty Cycle 2: THREC(MIN) = 0.422 * VSUP THDOM(MIN) = 0.284 * VSUP D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V ≤ VSUP ≤ 18 V D2 - - 0.581 LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION BUS LOAD RBUS AND CBUS 1.0 NF / 1.0 KΩ, 6.8 NF / 660 Ω, 10 NF / 500 Ω. MEASUREMENT THRESHOLDS. SEE Figure 21, PAGE 32. Duty Cycle 3: THREC(MAX) = 0.778 * VSUP THDOM(MAX) = 0.616 * VSUP D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V ≤ VSUP ≤ 18 V D3 0.417 - - Duty Cycle 4: THREC(MIN) = 0.389 * VSUP THDOM(MIN) = 0.251 * VSUP D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V ≤ VSUP ≤ 18 V D4 - - 0.590 LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE LIN Fast Slew Rate (Programming Mode) SRFAST - 20 - V/ μs LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS VSUP FROM 7.0 TO 18 V, BUS LOAD RBUS AND CBUS 1.0 NF / 1.0 KΩ, 6.8 NF / 660 Ω, 10 NF / 500 Ω. SEE Figure 20, PAGE 31. Propagation Delay and Symmetry (See Figure 20, page 31 and Figure 21, page 32) Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR tREC_PD tREC_SYM - -2.0 4.2 - 6.0 2.0 μs Bus Wake-up Deglitcher (LP VDD OFF and LP VDD ON modes) (See Figure 22, page 31 for LP VDD OFF Mode and Figure 23, page 32 for LP Mode) tPROPWL 42 70 95 μs Bus Wake-up Event Reported From LP VDD OFF Mode From LP VDD ON Mode tWAKE_LPVDD OFF tWAKE_LPVDD ON - 1.0 - - 1500 12 μs TXD Permanent Dominant State Delay (Guaranteed by design) tTXDDOM 0.65 1.0 1.35 s Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |