33903 datasheet(36/104 Pages) FREESCALE

36 / 104 page

VBAT

VSUP/1

S_in

I/O-1

I/O-0

Multiplexer

VDD-I_COPY

RM(*)

(*)Optional

A/D in

MCU

S_iddc

MUX-OUT

S_g3.3

Temp

VSENSE

S_g5

RSENSE 1.0 k

RMI

S_ir

S_in

VREF: 2.5 V

5V-CAN

S_I/O_att

All swicthes and resistor are configured and controlled via the SPI

RM: internal resistor connected when VREG current monitor is used

S_g3.3 and S_g5 for 5.0 V or 3.3 V VDD versions

S_iddc to select VDD regulator current copy

S_in1 for LP Mode resistor bridge disconnection

S_ir to switch on/off of the internal RMI resistor

S_I/O_att for I/O-0 and I/O-1 attenuation selection

buffer

5V-CAN

Analog Integrated Circuit Device Data

Freescale Semiconductor

33903/4/5

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

Figure 24. Analog Multiplexer Block Diagram

DGB (DGB) AND DEBUG MODE

Primary Function

It is an input used to set the device in Debug Mode. This is

achieved by applying a voltage between 8.0 and 10 V at the

DEBUG pin and then, powering up the device (See State

Diagram 40). When the device leaves the INIT Reset Mode

and enters into INIT Mode, it detects the voltage at the

DEBUG pin to be between a range of 8.0 to 10 V, and

activates the Debug Mode.

When Debug Mode is detected, no Watchdog SPI refresh

commands are necessary. This allows an easy debug of the

hardware and software routines (i.e. SPI commands).

When the device is in Debug Mode it is reported by the SPI

flag. While in Debug Mode, and the voltage at DBG pin falls

below the 8.0 to 10 V range, the Debug Mode is left, and the

device starts the watchdog operation, and expects the proper

watchdog refresh. The Debug Mode can be left by SPI. This

is recommended to avoid staying in Debug Mode when an

unwanted Debug Mode selection (FMEA pin) is present. The

SPI command has a higher priority than providing 8.0 to 10 V

at the DEBUG pin.

Secondary Function

The resistor connected between the DBG pin and the GND

selects the Fail-Safe Mode operation. DBG pin can also be

connected directly to GND (this prevents the usage of Debug

Mode).

Flexibility is provided to select SAFE output operation via

a resistor at the DBG pin or via a SPI command. The SPI

command has higher priority than the hardware selection via

Debug resistor.

When the Debug Mode is selected, the SAFE modes

cannot be configured via the resistor connected at DBG pin.

SAFE

Safe Output Pin

This pin is an output and is asserted low when a fault event

occurs. The objective is to drive electrical safe circuitry and

set the ECU in a known state, independent of the MCU and

SBC, once a failure has been detected.

The SAFE output structure is an open drain, without a pull-

up.

INTERRUPT (INT)

The INT output pin is asserted low or generates a low

pulse when an interrupt condition occurs. The INT condition

is enabled in the INT register. The selection of low level or

pulse and pulse duration are selected by SPI.

No current will flow inside the INT structure when VDD is

low, and the device is in LP VDD OFF Mode. This allows the

connection of an external pull-up resistor and connection of

an INT pin from other ICs without extra consumption in

unpowered mode.

33903 Datasheet(PDF) 36 Page - Freescale Semiconductor, Inc

33903 Datasheet(HTML) 36 Page - Freescale Semiconductor, Inc

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