| Electronic Components Datasheet Search |
|
33903 Datasheet(PDF) 16 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
33903 Datasheet(HTML) 16 Page - Freescale Semiconductor, Inc |
|
16 / 104 page ![]() Analog Integrated Circuit Device Data 16 Freescale Semiconductor 33903/4/5 PIN CONNECTIONS 39 20 20 N/A 22 22 VSENSE Input Sense input Direct battery voltage input sense. A serial resistor is required to limit the input current during high voltage transients. 40 21 21 N/A N/A N/A I/O-1 Input/ Output Input Output 1 Configurable pin as an input or output, for connection to external circuitry (switched or small load). The voltage level can be read by the SPI and the MUX output pin. The input can be used as a programmable Wake-Up input in (LP) Mode. It can be used in association with I/O-0 for a cyclic sense function in (LP) Mode. 41 22 22 22 23 23 RST Output Reset Output (Active LOW) This is the device reset output whose main function is to reset the MCU. This pin has an internal pull-up to VDD. The reset input voltage is also monitored in order to detect external reset and safe conditions. 42 23 23 23 24 24 INT Output Interrupt Output (Active LOW) This output is asserted low when an enabled interrupt condition occurs. This pin is an open drain structure with an internal pull up resistor to VDD. 43 24 24 24 25 25 CS Input Chip Select (Active LOW) Chip select pin for the SPI. When the CS is low, the device is selected. In (LP) Mode with VDD ON, a transition on CS is a Wake-Up condition 44 25 25 25 26 26 SCLK Input Serial Data Clock Clock input for the Serial Peripheral Interface (SPI) of the device 45 26 26 26 27 27 MOSI Input Master Out/ Slave In SPI data received by the device 46 27 27 27 28 28 MISO Output Master In/ Slave Out SPI data sent to the MCU. When the CS is high, MISO is high-impedance 47 28 28 28 29 29 VDD Output Voltage Digital Drain 5.0 or 3.3 V output pin of the main regulator for the Microcontroller supply. 48 29 29 29 30 30 TXD Input Transmit Data CAN bus transmit data input. Internal pull-up to VDD 49 30 30 30 31 31 RXD Output Receive Data CAN bus receive data output 50 31 31 N/A 32 32 VE Voltage Emitter Connection to the external PNP path transistor. This is an intermediate current supply source for the VDD regulator 51 32 32 N/A 1 1 VB Output Voltage Base Base output pin for connection to the external PNP pass transistor EX PAD EX PAD EX PAD EX PAD EX PAD EX PAD GND Ground Ground Ground Table 2. 33903/4/5 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 34. 54 Pin 33905D 32 Pin 33905S 32 Pin 33904 32 Pin 33903 32 Pin 33903D 32 Pin 33903S Pin Name Pin Function Formal Name Definition |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |