33903 datasheet(69/104 Pages) FREESCALE

69 / 104 page

Table 16. Initialization Watchdog Registers, INIT watchdog (note: register can be written only in INIT Mode)

MOSI First Byte [15-8]

[b_15 b_14] 0_0110 [P/N]

MOSI Second Byte, bits 7-0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

01 00 _ 110 P

WD2INT

MCU_OC

OC-TIM

WD Safe

WD_spi[1]

WD_spi[0]

WD N/Win

Crank

Default state

Condition for default

POR

Analog Integrated Circuit Device Data

Freescale Semiconductor

33903/4/5

SERIAL PERIPHERAL INTERFACE

DETAIL OF CONTROL BITS AND REGISTER MAPPING

Bit

Description

WD2INT - Select the maximum time delay between INT occurrence and INT source read SPI command

Function disable. No constraint between INT occurrence and INT source read.

INT source read must occur before the remaining of the current watchdog period plus 2 complete watchdog periods.

b6, b5

MCU_OC, OC-TIM - In LP VDD ON, select watchdog refresh and VDD current monitoring functionality. VDD_OC_LP threshold is defined in device

electrical parameters (approx 1.5 mA)

In LP Mode, when watchdog is not selected

no watchdog

+ 00

In LP VDD ON Mode, VDD over-current has no effect

no watchdog

+ 01

In LP VDD ON Mode, VDD over-current has no effect

no watchdog

+ 10

In LP VDD ON Mode, VDD current > VDD_OC_LP threshold for a time > 100 μs (typically) is a Wake-Up event

no watchdog

+ 11

In LP VDD ON Mode, VDD current > VDD_OC_LP threshold for a time > I_mcu_OC is a Wake-Up event. I_mcu_OC time is selected in Timer register

(selection range from 3.0 to 32 ms)

In LP Mode when watchdog is selected

watchdog +

In LP VDD ON Mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command.

watchdog +

In LP VDD ON Mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command.

watchdog +

In LP VDD ON Mode, VDD over-current for a time > 100 μs (typically) is a Wake-Up event.

watchdog +

In LP VDD ON Mode, VDD current > VDD_OC_LP threshold for a time < I_mcu_OC is a watchdog refresh condition. VDD current > VDD_OC_LP

threshold for a time > I_mcu_OC is Wake-Up event. I_mcu_OC time is selected in Timer register (selection range from 3.0 to 32 ms)

WD Safe - Select the activation of the SAFE pin low, at first or second consecutive RESET pulse

SAFE pin is set low at the time of the RESET pin low activation

SAFE pin is set low at the second consecutive time RESET pulse

b3, b2

WD_spi[1] WD_spi[0] - Select the Watchdog (watchdog) Operation

Simple Watchdog selection: watchdog refresh done by a 8 bits or 16 bits SPI

Enhanced 1: Refresh is done using the Random Code, and by a single 16 bits.

Enhanced 2: Refresh is done using the Random Code, and by two 16 bits command.

Enhanced 4: Refresh is done using the Random Code, and by four 16 bits command.

WD N/Win - Select the Watchdog (watchdog) Window or Timeout operation

Watchdog operation is TIMEOUT, watchdog refresh can occur anytime in the period

Watchdog operation is WINDOW, watchdog refresh must occur in the open window (second half of period)

33903 Datasheet(PDF) 69 Page - Freescale Semiconductor, Inc

33903 Datasheet(HTML) 69 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL