33903 datasheet(76/104 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33903/4/5

SERIAL PERIPHERAL INTERFACE

DETAIL OF CONTROL BITS AND REGISTER MAPPING

Prior to enter in LP VDD ON or LP VDD OFF, the Wake-Up

flags must be cleared or read.

This is done by the following SPI commands (See Table

37, Device Flag, I/O Real Time and Device Identification):

0xE100 for CAN Wake-Up clear

0xE380 for I/O Wake-Up clear

0xE700 for LIN1 Wake-Up clear

0xE900 for LIN2 Wake-Up clear

If Wake-Up flags are not cleared, the device will enter into

the selected LP Mode and immediately Wake-Up. In addition,

the CAN failure flags (i.e. CAN_F and CAN_UF) must be

cleared in order to meet the low power current consumption

specification. This is done by the following SPI command:

0xE180 (read CAN failure flags)

When the device is in LP VDD ON Mode, the Wake-Up by

a SPI command uses a write to “Normal Request Mode”,

0x5C10.

Mode Register Features

The mode register includes specific functions and a “global

SPI command” that allow the following:

- read device current mode

- read device Debug status

- read state of SAFE pin

- leave Debug state

- release or turn off SAFE pin

- read a 3 bit Random Code to enter in LP Mode

These global commands are built using the MODE register

address bit [13-9], along with several combinations of bit [15-

14] and bit [7]. Note, bit [8] is always set to 1.

Entering into LP Mode using Random Code

- LP Mode using Random Code must be selected in INIT

Mode via bit 7 of the INIT MISC register.

- In Normal Mode, read the Random Code using 0x1D00 or

0x1D80 command. The 3 Random Code bits are available on

MISO bits 2,1 and 0.

- Write LP Mode by inverting the 3 random bits.

Example - Select LP VDD OFF without cyclic sense and

FWU:

1. in hex: 0x5C60 to enter in LP VDD OFF Mode without

using the 3 random code bits.

2. if Random Code is selected, the commands are:

- Read Random Code: 0x1D00 or 0x1D80,

MISO report in binary: bits 15-8, bits 7-3, Rnd_[2], Rnd_[1],

Rnd_[0].

- Write LP VDD OFF Mode, using Random Code inverted:

in binary: 0101 1100 0110 0 Rnd_b[2], Rnd_b[1], Rnd_b[0].

Table 28 summarizes these commands

Table 28. Device Modes

Global commands and effects

Read device current mode, Leave debug mode.

Keep SAFE pin as is.

MOSI in hexadecimal: 1D 00

MOSI

bits 15-14

bits 13-9

bit 8

bit 7

bits 6-0

01 110

000 0000

MISO

bit 15-8

bit 7-3

bit 2-0

Fix Status

device current mode

Random code

Read device current mode

Release SAFE pin (turn OFF).

MOSI in hexadecimal: 1D 80

MOSI

bits 15-14

bits 13-9

bit 8

bit 7

bits 6-0

01 110

000 0000

MISO

bit 15-8

bit 7-3

bit 2-0

Fix Status

device current mode

Random code

Read device current mode, Leave debug mode.

Keep SAFE pin as is.

MOSI in hexadecimal: DD 00

MISO reports Debug and SAFE state (bits 1,0)

MOSI

bits 15-14

bits 13-9

bit 8

bit 7

bits 6-0

01 110

000 0000

MISO

bit 15-8

bit 7-3

bit 2

bit 1

bit 0

Fix Status

device current mode

SAFE

DEBUG

Read device current mode, Keep DEBUG mode

Release SAFE pin (turn OFF).

MOSI in hexadecimal: DD 80

MISO reports Debug and SAFE state (bits 1,0)

MOSI

bits 15-14

bits 13-9

bit 8

bit 7

bits 6-0

01 110

000 0000

MISO

bit 15-8

bit 7-3

bit 2

bit 1

bit 0

Fix Status

device current mode

SAFE

DEBUG

33903 Datasheet(PDF) 76 Page - Freescale Semiconductor, Inc

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