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33903 Datasheet(PDF) 74 Page - Freescale Semiconductor, Inc |
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33903 Datasheet(HTML) 74 Page - Freescale Semiconductor, Inc |
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74 / 104 page  Table 22. Timer Register C, Watchdog LP Mode or Flash Mode and Forced Wake-up Timer, TIM_C MOSI First Byte [15-8] [b_15 b_14] 01_100 [P/N] MOSI Second Byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 100 P WD-LP-F[3] WD-LP-F[2] WD-LP-F[1] WD-LP-F[0] FWU[3] FWU[2] FWU[1] FWU[0] Default state 0 0 0 0 0 0 0 0 Condition for default POR Table 23. Typical Timing Values Watchdog in LP VDD ON Mode (ms) b7 b6, b5, b4 000 001 010 011 100 101 110 111 0 12 24 48 96 192 384 768 1536 1 16 32 64 128 256 512 1024 2048 Watchdog in Flash Mode (ms) b7 b6, b5, b4 000 001 010 011 100 101 110 111 0 48 (def) 96 192 384 768 1536 3072 6144 1 256 512 1024 2048 4096 8192 16384 32768 Forced Wake-up (ms) b3 b2, b1, b0 000 001 010 011 100 101 110 111 0 48 (def) 96 192 384 768 1536 3072 6144 1 64 128 258 512 1024 2048 4096 8192 Analog Integrated Circuit Device Data 74 Freescale Semiconductor 33903/4/5 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING |
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