33903 datasheet(71/104 Pages) FREESCALE

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Table 18. Initialization Miscellaneous Functions, INIT MISC (Note: Register can be written only in INIT Mode)

MOSI First Byte [15-8]

[b_15 b_14] 0_1000 [P/N]

MOSI Second Byte, bits 7-0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

01 01_ 000 P

LPM w RNDM

SPI parity

INT pulse

INT width

INT flash

Dbg Res[2]

Dbg Res[1]

Dbg Res[0]

Default state

Condition for default

POR

Bit

Description

LPM w RNDM - This enables the usage of random bits 2, 1 and 0 of the MODE register to enter into LP VDD OFF or LP VDD ON.

Function disable: the LP Mode can be entered without usage of Random Code

Function enabled: the LP Mode is entered using the Random Code

SPI parity - Select usage of the parity bit in SPI write operation

Function disable: the parity is not used. The parity bit must always set to logic 0.

Function enable: the parity is used, and parity must be calculated.

INT pulse -Select INT pin operation: low level pulse or low level

INT pin will assert a low level pulse, duration selected by bit [b4]

INT pin assert a permanent low level (no pulse)

INT width - Select the INT pulse duration

INT pulse duration is typically 100

μs. Ref. to dynamic parameter table for exact value.

INT pulse duration is typically 25

μs. Ref. to dynamic parameter table for exact value.

INT flash - Select INT pulse generation at 50% of the Watchdog Period in Flash Mode

Function disable

Function enable: an INT pulse will occur at 50% of the Watchdog Period when device in Flash Mode.

b2, b1, b0

Dbg Res[2], Dbg Res[1], Dbg Res[0] - Allow verification of the external resistor connected at DBG pin. Ref. to parametric table for resistor range

value.(33)

0xx

Function disable

100

100 verification enable: resistor at DBG pin is typically 68 kohm (RB3) - Selection of SAFE Mode B3

101

101 verification enable: resistor at DBG pin is typically 33 kohm (RB2 - Selection of SAFE Mode B2

110

110 verification enable: resistor at DBG pin is typically 15 kohm (RB1) - Selection of SAFE Mode B1

111

111 verification enable: resistor at DBG pin is typically 0 kohm (RA) - Selection of SAFE Mode A

Notes

33.

Bits b2,1 and 0 allow the following operation:

First, check the resistor device has detected at the DEBUG pin. If the resistor is different, bit 5 (Debug resistor) is set in INTerrupt

Second, over write the resistor decoded by device, to set the SAFE Mode operation by SPI. Once this function is selected by bit 2 = 1,

this selection has higher priority than “hardware”, and device will behave according to b2,b1 and b0 setting

Analog Integrated Circuit Device Data

Freescale Semiconductor

33903/4/5

SERIAL PERIPHERAL INTERFACE

DETAIL OF CONTROL BITS AND REGISTER MAPPING

33903 Datasheet(PDF) 71 Page - Freescale Semiconductor, Inc

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