 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
33903 Datasheet(PDF) 77 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
33903 Datasheet(HTML) 77 Page - Freescale Semiconductor, Inc |
|
|
77 / 104 page  Analog Integrated Circuit Device Data Freescale Semiconductor 77 33903/4/5 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING The Tables below describes MISO bits 7-0, used to decode the device’s current mode. Table 29. MISO bits 7-3 Device current mode, any of the above command b7, b6, b5, b4, b3 MODE 0 0000 INIT 0 0001 FLASH 0 0010 Normal Request 0 0011 Normal Mode The Table below describes the SAFE and DEBUG bit decoding. Table 30. SAFE and DEBUG status SAFE and DEBUG bits b1 description 0 SAFE pin OFF, not activated 1 SAFE pin ON, driver activated. b0 description 0 Debug Mode OFF 1 Debug Mode Active Table 31. Regulator Register MOSI First Byte [15-8] [b_15 b_14] 01_111 [P/N] MOSI Second Byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 01_ 111 P VAUX[1] VAUX[0] - 5V-can[1] 5V-can[0] VDD bal en VDD bal auto VDD OFF en Default state 0 0 N/A 0 0 N/A N/A N/A Condition for default POR POR Bits Description b7 b6 VAUX[1], VAUX[0] - Vauxilary regulator control 00 Regulator OFF 01 Regulator ON. Under-voltage (UV) and Over-current (OC) monitoring flags not reported. VAUX is disabled when UV or OC detected after 1.0 ms blanking time. 10 Regulator ON. Under-voltage (UV) and over-current (OC) monitoring flags active. VAUX is disabled when UV or OC detected after 1.0 ms blanking time. 11 Regulator ON. Under-voltage (UV) and over-current (OC) monitoring flags active. VAUX is disabled when UV or OC detected after 25 μs blanking time. b4 b3 5 V-can[1], 5 V-can[0] - 5V-CAN regulator control 00 Regulator OFF 01 Regulator ON. Thermal protection active. Under-voltage (UV) and over-current (OC) monitoring flags not reported. 1.0 ms blanking time for UV and OC detection. 10 Regulator ON. Thermal protection active. Under-voltage (UV) and over-current (OC) monitoring flags active. 1.0 ms blanking time for UV and OC detection. 11 Regulator ON. Thermal protection active. Under-voltage (UV) and over-current (OC) monitoring flags active. 5 V-CAN disable when UV or OC detected after 25 μs blanking time. b2 VDD bal en - Control bit to Enable the VDD external ballast transistor 0 External VDD ballast disable 1 External VDD ballast Enable b1 VDD bal auto - Control bit to automatically Enable the VDD external ballast transistor, if VDD is > typically 60 mA 0 Disable the automatic activation of the external ballast 1 Enable the automatic activation of the external ballast, if VDD > typically 60 mA b0 VDD OFF en - Control bit to allow transition into LP VDD OFF Mode (to prevent VDD turn OFF) 0 Disable Usage of LP VDD OFF Mode 1 Enable Usage of LP VDD OFF Mode REGULATOR, CAN, I/O, INT AND LIN REGISTERS |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
