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33903 Datasheet(PDF) 55 Page - Freescale Semiconductor, Inc

Part # 33903
Description  SBC Gen2 with CAN High Speed and LIN Interface
PDF  104 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

33903 Datasheet(HTML) 55 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
55
33903/4/5
CAN INTERFACE
CAN INTERFACE DESCRIPTION
When the CAN interface is in Normal Mode, the driver has
two states: recessive or dominant. The driver state is
controlled by the TXD pin. The bus state is reported through
the RXD pin.
When TXD is high, the driver is set in the recessive state,
and CANH and CANL lines are biased to the voltage set with
5 V-CAN divided by 2, or approx. 2.5 V.
When TXD is low, the bus is set into the dominant state,
and CANL and CANH drivers are active. CANL is pulled low
and CANH is pulled high.
The RXD pin reports the bus state: CANH minus the CANL
voltage is compared versus an internal threshold (a few
hundred mV).
If “CANH minus CANL” is below the threshold, the bus is
recessive and RXD is set high.
If “CANH minus CANL” is above the threshold, the bus is
dominant and RXD is set low.
The SPLIT pin is active and provides a 2.5 V biasing to the
SPLIT output.
TXD/RXD Mode and Slew Rate Selection
The CAN signal slew rate selection is done via the SPI. By
default and if no SPI is used, the device is in the fastest slew
rate. Three slew rates are available. The slew rate controls
the recessive to dominant, and dominant to recessive
transitions. This also affects the delay time from the TXD pin
to the bus and from the bus to the RXD. The loop time is thus
affected by the slew rate selection.
Minimum Baud Rate
The minimum baud rate is determined by the shortest TXD
permanent dominant timing detection. The maximum number
of consecutive dominant bits in a frame is 12 (6 bits of active
error flag and its echo error flag).
The shortest TXD dominant detection time of 300
μs lead
to a single bit time of: 300
μs / 12 = 25 μs.
So the minimum Baud rate is 1 / 25
μs = 40 kBaud.
Sleep Mode
Sleep Mode is a reduced current consumption mode.
CANH and CANL drivers are disabled and CANH and CANL
lines are terminated to GND via the RIN resistor, the SPLIT
pin is high-impedance. In order to monitor bus activities, the
CAN Wake-Up receiver can be enabled. It is supplied
internally from VSUP/2.
Wake-up events occurring on the CAN bus pin are
reporting by dedicated flags in SPI and by INT pulse, and
results in a device Wake-Up if the device was in LP Mode.
When the device is set back into Normal Mode, CANH and
CANL are set back into the recessive level. This is illustrated
in Figure 36.
.
CANL
CANH
TXD
RXD
2.5 V
CANL-DOM
CANH-DOM
CANL/CANH-REC
2.5 V
High ohmic termination (50 kohm) to GND
SPLIT
Dominant state
Recessive state
Bus Driver
Receiver
(bus dominant set by other IC)
High-impedance
Normal or Listen Only Mode
Normal or Listen Only Mode
Go to sleep,
CANH-CANL
Sleep or Stand-by Mode
Figure 36. Bus Signal in TXD/RXD and LP Mode
Wake-up
When the CAN interface is in Sleep Mode with Wake-Up
enabled, the CAN bus traffic is detected. The CAN bus Wake-
Up is a pattern Wake-Up. The Wake-Up by the CAN is
enabled or disabled via the SPI.



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