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33903 Datasheet(PDF) 80 Page - Freescale Semiconductor, Inc |
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33903 Datasheet(HTML) 80 Page - Freescale Semiconductor, Inc |
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80 / 104 page ![]() Table 34. INT Register MOSI First byte [15-8] [b_15 b_14] 10_010 [P/N] MOSI Second Byte, bits 7-0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01 10_ 010P CAN failure MCU req LIN2 fail LIN1fail I/O SAFE - Vmon Default state 0 0 0 0 0 0 0 0 Condition for default POR Bits Description b7 CAN failure - control bit for CAN failure INT (CANH/L to GND, VDD or VSUP, CAN over-current, Driver Over Temp, TXD-PD, RXD-PR, RX2HIGH, and CANBUS Dominate clamp) 0 INT disable 1 INT enable. b6 MCU req - Control bit to request an INT. INT will occur once when the bit is enable 0 INT disable 1 INT enable. b5 LIN2 fail - Control bit to enable INT when of failure on LIN2 interface 0 INT disable 1 INT enable. b4 LIN/1 fail - Control bit to enable INT when of failure on LIN1 interface 0 INT disable 1 INT enable. b3 I/O - Bit to control I/O interruption: I/O failure 0 INT disable 1 INT enable. b2 SAFE - Bit to enable INT when of: Vaux over-voltage, VDD over-voltage, VDD Temp pre warning, VDD under-voltage(36), SAFE resistor mismatch, RST terminal short to VDD, MCU request INT.(37) 0 INT disable 1 INT enable. b0 VMON - enable interruption by voltage monitoring of one of the voltage regulator: VAUX, 5 V-CAN, VDD (IDD Over-current, VSUV, VSOV, VSENSELOW, 5V-CAN low or thermal shutdown, VAUX low or VAUX over-current 0 INT disable 1 INT enable. Notes 36. If VDD under-voltage is set to 70% of VDD, see bits b6 and b5 in Table 15 on page 68. 37. Bit 2 is used in conjunction with bit 6. Both bit 6 and bit 2 must be set to 1 to activate the MCU INT request. Analog Integrated Circuit Device Data 80 Freescale Semiconductor 33903/4/5 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING |
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