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33903 Datasheet(PDF) 63 Page - Freescale Semiconductor, Inc

Part # 33903
Description  SBC Gen2 with CAN High Speed and LIN Interface
PDF  104 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

33903 Datasheet(HTML) 63 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
63
33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OPERATION
DETAIL OPERATION
BITS 15, 14 AND 8 FUNCTIONS
Table 10 summarizes the various SPI operation, depending upon bit 15, 14, and 8.
Table 10. SPI Operations (bits 8, 14 & 15)
Control Bits MOSI[15-14], C1-C0
Type of Command
Parity/Next
MOSI[8] P/N
Note for Bit 8 P/N
00
Read back of register
content and block (CAN,
I/O, INT, LINs) real time
state. See Table 37.
1
Bit 8 must be set to 1, independently of the parity function
selected or not selected.
01
Write to register
address, to control the
device operation
0
If bit 8 is set to “0”: means parity not selected OR
parity is selected AND parity = 0
1
if bit 8 is set to “1”: means parity is selected AND parity = 1
10
Reserved
11
Read of device flags
form a register address
1
Bit 8 must be set to 1, independently of the parity function
selected or not selected.
BITS 13-9 FUNCTIONS
The device contains several registers coded on five bits
(bits 13 to 9).
Each register controls or reports part of the device’s
function. Data can be written to the register to control the
device operation or to set the default value or behavior.
Every register can also be read back in order to ensure
that it’s content (default setting or value previously written) is
correct.
In addition, some of the registers are used to report device
flags.
Device Status on MISO
When a write operation is performed to store data or
control bits into the device, the MISO pin reports a 16 bit fixed
device status composed of 2 bytes: Device Fixed Status (bits
15 to 8) + extended Device Status (bits 7 to 0). In a read
operation, MISO will report the Fixed device status (bits 15 to
8) and the next eight bits will be the content of the selected
register.
REGISTER ADRESS TABLE
Table 11 is a list of device registers and addresses, coded
with bits 13 to 9.
Table 11. Device Registers with Corresponding Address
Address
MOSI[13-9]
A4...A0
Description
Quick Ref.
Name
Functionality
0_0000
Analog Multiplexer
MUX
1) Write “device control bits” to register address.
2) Read back register “control bits”
0_0001
Memory byte A
RAM_A
1) Write “data byte” to register address.
2) Read back “data byte” from register address
0_0010
Memory byte B
RAM_B
0_0011
Memory byte C
RAM_C
0_0100
Memory byte D
RAM_D
0_0101
Initialization Regulators
Init REG
1) Write “device initialization control bits” to register address.
2) Read back “initialization control bits” from register address
0_0110
Initialization Watchdog
Init watchdog
0_0111
Initialization LIN and I/O
Init LIN I/O
0_1000
Initialization Miscellaneous functions
Init MISC
0_1001
Specific modes
SPE_MODE
1) Write to register to select device Specific mode, using “Inverted
Random Code”.
2) Read “Random Code”



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