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33903 Datasheet(PDF) 35 Page - Freescale Semiconductor, Inc

Part # 33903
Description  SBC Gen2 with CAN High Speed and LIN Interface
PDF  104 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

33903 Datasheet(HTML) 35 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
35
33903/4/5
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
VAUX is controlled via the SPI, and can be turned ON or
OFF. VAUX low threshold detection and over-current
information will disable VAUX, and are reported in the SPI and
can generate INT.
VAUX is OFF by default and must be turned ON by the SPI.
UNDER-VOLTAGE RESET AND RESET FUNCTION
(RST)
The RESET pin is an open drain structure with an internal
pull-up resistor. The LS driver has limited current capability
when asserted low, in order to tolerate a short to 5.0 V. The
RESET pin voltage is monitored in order to detect failure (e.g.
RESET pin shorted to 5.0 V or GND).
The RESET pin reports an under-voltage condition to the
MCU at the VDD pin, as well as failure in the watchdog
refresh operation. VDD under-voltage reset also operates in
LP VDD ON Mode.
Two VDD under-voltage thresholds are included. The
upper (typically 4.65 V, RST-TH1-5) can lead to a Reset or an
Interrupt. This is selected by the SPI. When “RST-TH2-5“is
selected, in Normal Mode, an INT is asserted when VDD falls
below “RST-TH1-5“, then, when VDD falls below “RST-TH2-5” a
Reset will occur. This will allow the MCU to operate in a
degraded mode (i.e., with 4.0 V VDD).
I/O PINS (I/O-0: I/O-3)
I/Os are configurable input/output pins. They can be used
for small loads or to drive external transistors. When used as
output drivers, the I/Os are either a HS or LS type. They can
also be set to high-impedance. I/Os are controlled by the SPI
and at power on, the I/Os are set as inputs. They include
over-load protection by temperature or excess of a voltage
drop.
When I/O-0/-1/-2/-3 voltage is greater than VSUP/2
voltage, the leakage current (II/O_LEAK) parameter is not
applicable
• I/O-0 and I/O-1 will have current flowing into the device
through three diodes limited by an 80 kOhm resistor (in
series).
• I/O-2 and I/O-3 will have unlimited current flowing into the
device through one diode.
In LP Mode, the state of the I/O can be turned ON or OFF,
with extremely low power consumption (except when there is
a load). Protection is disabled in LP Mode.
When cyclic sense is used, I/O-0 is the HS/LS switch, I/O-
1, -2 and -3 are the wake inputs.
I/O-2 and I/O-3 pins share the LIN Master pin function.
VSENSE INPUT (VSENSE)
This pin can be connected to the battery line (before the
reverse battery protection diode), via a serial resistor and a
capacitor to GND. It incorporates a threshold detector to
sense the battery voltage and provide a battery early
warning. It also includes a resistor divider to measure the
VSENSE voltage via the MUX-OUT pin.
MUX-OUTPUT (MUXOUT)
The MUX-OUT pin (Figure 24) delivers an analog voltage
to the MCU A/D input. The voltage to be delivered to MUX-
OUT is selected via the SPI, from one of the following
functions: VSUP/1, VSENSE, I/O-0, I/O-1, Internal 2.5 V
reference, die temperature sensor, VDD current copy.
Voltage divider or amplifier is inserted in the chain, as
shown in Figure 24.
For the VDD current copy, a resistor must be added to the
MUX-OUT pin, to convert current into voltage. Device
includes an internal 2.0 k resistor selectable by the SPI.
Voltage range at MUX-OUT is from GND to VDD. It is
automatically limited to VDD (max 3.3 V for 3.3 V part
numbers).
The MUX-OUT buffer is supplied from 5 V-CAN regulator,
so the 5 V-CAN regulator must be ON in order to have:
1) MUX-OUT functionality and
2) SPI selection of the analog function.
If the 5 V-CAN is OFF, the MUX-OUT voltage is near GND
and the SPI command that selects one of the analog inputs
is ignored.
Delay must be respected between SPI commands for 5 V-
CAN turned ON and SPI to select MUX-OUT function. The
delay depends mainly upon the 5 V-CAN capacitor and load
on 5 V-CAN.
The delay can be estimated using the following formula:
delay = C(5 V-CAN) x U (5.0 V) / I_lim 5 V-CAN.
C = cap at 5 V-CAN regulator, U = 5.0 V,
I_LIM 5 V-CAN = min current limit of 5 V-CAN regulator
(parameter 5 V-C ILIM).



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