33903 datasheet(41/104 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33903/4/5

FUNCTIONAL DEVICE OPERATION

MODE CHANGE

“SECURED SPI” DESCRIPTION:

A request is done by a SPI command, the device provide

on MISO an unpredictable “random code”. Software must

perform a logical change on the code and return it to the

device with the new SPI command to perform the desired

action.

The “random code” is different at every exercise of the

secured procedure and can be read back at any time.

The secured SPI uses the Special MODE register for the

following transitions:

- from Normal Mode to INT Mode

- from Normal Mode to Flash Mode

- from Normal Mode to Reset Mode (reset request).

“Random code” is also used when the “advance

watchdog” is selected.

CHANGING OF DEVICE CRITICAL PARAMETERS

Some critical parameters are configured one time at

device power on only, while the batfail flag is set in the INIT

Mode. If a change is required while device is no longer in INIT

Mode, device must be set back in INIT Mode using the “SPI

secure” procedure.

WATCHDOG OPERATION

IN NORMAL REQUEST MODE

In Normal Request Mode, the device expects to receive a

watchdog configuration before the end of the normal request

time out period. This period is reset to a long (256 ms) after

power on and when BATFAIL is set.

The device can be configured to a different (shorter) time

out period which can be used after Wake-Up from LP VDD on

Mode.

After a software watchdog reset, the value is restored to

256 ms, in order to allow for a complete software initialization,

similar to a device power up.

In Normal Request Mode the watchdog operation is

“timeout” only and can be triggered/observed any time within

the period.

WATCHDOG TYPE SELECTION

Three types of watchdog operation can be used:

- Window watchdog (default)

- Timeout operation

- Advanced

The selection of watchdog is performed in INIT Mode. This

is done after device power up and when the BATFAIL flag is

set. The Watchdog configuration is done via the SPI, then the

Watchdog Mode selection content is locked and can be

changed only via a secured SPI procedure.

Window Watchdog Operation

The window watchdog is available in Normal Mode only.

The watchdog period selection can be kept (SPI is selectable

in INIT Mode), while the device enters into LP VDD ON Mode.

The watchdog period is reset to the default long period after

BATFAIL.

The period and the refresh of watchdog are done by the

SPI. A refresh must be done in the open window of the

period, which starts at 50% of the selected period and ends

at the end of the period.

If the watchdog is triggered before 50%, or not triggered

before end of period, a reset has occurred. The device enters

into Reset Mode.

Watchdog in Debug Mode

When the device is in Debug Mode (entered via the DBG

pin), the watchdog continues to operate but does not affect

the device operation by asserting a reset. For the user,

operation appears without the watchdog.

When Debug Mode is set by software (SPI Mode reg), the

watchdog period starts at the end of the SPI command.

When Debug Mode is set by hardware (DBG pin below 8-

10 V), the device enters into Reset Mode.

Watchdog in Flash Mode

During Flash Mode, watchdog can be set to a long timeout

period. Watchdog is timeout only and an INT pulse can be

generated at 50% of the time window.

Advance Watchdog Operation

When the Advance watchdog is selected (at INIT Mode),

the refresh of the watchdog must be done using a random

number and with 1, 2, or 4 SPI commands. The number for

the SPI command is selected in INIT Mode.

The software must read a random byte from the device,

and then must return the random byte inverted to clear the

watchdog. The random byte write can be performed in 1, 2,

or 4 different SPI commands.

If one command is selected, all eight bits are written at

once.

If two commands are selected, the first write command

must include four of the eight bits of the inverted random byte.

The second command must include the next four bits. This

completes the watchdog refresh.

If four commands are selected, the first write command

must include two of the eight bits of the inverted random byte.

The second command must include the next two bits, the 3rd

command must include the next two, and the last command,

33903 Datasheet(PDF) 41 Page - Freescale Semiconductor, Inc

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