33903 datasheet(64/104 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33903/4/5

SERIAL PERIPHERAL INTERFACE

DETAIL OPERATION

COMPLETE SPI OPERATION

Table 12 is a compiled view of all the SPI capabilities and

options. Both MOSI and MISO information are described.

Table 12. SPI Capabilities with Options

Type of Command

MOSI/

MISO

Control bits

[15-14]

Address

[13-9]

Parity/Next

bits [8]

Bit 7

Bits [6-0]

Read back of “device control bits” (MOSI bit 7 = 0)

Read specific device information (MOSI bit 7 = 1)

MOSI

address

000 0000

MISO

Device Fixed Status (8 bits)

MOSI

address

000 0000

MISO

Device Fixed Status (8 bits)

Device ID and I/Os state

Write device control bit to address selected by bits

(13-9).

MISO return 16 bits device status

MOSI

address

(note)

Control bits

MISO

Device Fixed Status (8 bits)

Device Extended Status (8 bits)

Reserved

MOSI

Reserved

MISO

Reserved

Read device flags and Wake-Up flags, from

MISO return fixed device status (bit 15-8) + flags

from the selected address and sub-address.

MISO

address

Reserved

Read of device flags form a register address,

and sub address LOW (bit 7)

MOSI

Device Fixed Status (8 bits)

Flags

MISO

address

Read of device flags form a register address,

and sub address HIGH (bit 7)

MOSI

Device Fixed Status (8 bits)

Flags

Note: P = 0 if parity bit is not selected or parity = 0. P = 1 if parity

is selected and parity = 1.

PARITY BIT 8

Calculation

The parity is used for the write-to-register command (bit

15,14 = 01). It is calculated based on the number of logic one

contained in bits 15-9,7-0 sequence (this is the entire 16 bits

of the write command except bit 8).

Bit 8 must be set to 0 if the number of 1 is odd.

Bit 8 must be set to 1if the number of 1 is even.

Examples 1:

MOSI [bit 15-0] = 01 00 011 P 01101001, P should be 0,

because the command contains 7 bits with logic 1.

Thus the Exact command will then be:

MOSI [bit 15-0] = 01 00 011 0 01101001

0_1010

Timer_A: watchdog & LP MCU consumption

TIM_A

1) Write “timing values” to register address.

2) Read back register “timing values”

0_1011

Timer_B: Cyclic Sense & Cyclic Interrupt

TIM_B

0_1100

Timer_C: watchdog LP & Forced Wake-up

TIM_C

0_1101

Watchdog Refresh

watchdog

Watchdog Refresh Commands

0_1110

Mode register

MODE

1) Write to register to select LP Mode, with optional “Inverted Random

code” and select Wake-Up functionality

2) Read operations:

Read back device “Current Mode”

Read “Random Code”,

Leave “Debug Mode”

0_1111

Regulator Control

REG

1) Write “device control bits” to register address, to select device

operation.

2) Read back register “control bits”.

3) Read device flags from each of the register addresses.

1_0000

CAN interface control

CAN

1_0001

Input Output control

I/O

1_0010

Interrupt Control

Interrupt

1_0011

LIN1 interface control

LIN1

1_0100

LIN2 interface control

LIN2

Table 11. Device Registers with Corresponding Address

33903 Datasheet(PDF) 64 Page - Freescale Semiconductor, Inc

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