33903 datasheet(79/104 Pages) FREESCALE

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Table 33. I/O Register

MOSI First byte [15-8]

[b_15 b_14] 10_001 [P/N]

MOSI Second Byte, bits 7-0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

01 10_ 001P

I/O-3 [1]

I/O-3 [0]

I/O-2 [1]

I/O-2 [0]

I/O-1 [1]

I/O-1 [0]

I/O-0 [1]

I/O-0 [0]

Default state

Condition for default

POR

Bits

Description

b7 b6

I/O-3 [1], I/O-3 [0] - I/O-3 pin operation

I/O-3 driver disable, Wake-up capability disable

I/O-3 driver disable, Wake-up capability enable.

I/O-3 HS driver enable.

b5 b4

I/O-2 [1], I/O-2 [0] - I/O-2 pin operation

I/O-2 driver disable, Wake-up capability disable

I/O-2 driver disable, Wake-up capability enable.

I/O-2 HS driver enable.

b3 b2

I/O-1 [1], I/O-1 [0] - I/O-1 pin operation

I/O-1 driver disable, Wake-up capability disable

I/O-1 driver disable, Wake-up capability enable.

I/O-1 LS driver enable.

I/O-1 HS driver enable.

b1 b0

I/O-0 [1], I/O-0 [0] - I/O-0 pin operation

I/O-0 driver disable, Wake-up capability disable

I/O-0 driver disable, Wake-up capability enable.

I/O-0 LS driver enable.

I/O-0 HS driver enable.

Analog Integrated Circuit Device Data

Freescale Semiconductor

33903/4/5

SERIAL PERIPHERAL INTERFACE

DETAIL OF CONTROL BITS AND REGISTER MAPPING

33903 Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc

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